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/libcpu/mips/gs232/
A Dcache.c116 while (start < end) in invalidate_writeback_dcache_all()
130 while (start <end) in invalidate_writeback_dcache()
142 while (start < end) in invalidate_icache_all()
153 while (start <end) in invalidate_dcache_all()
182 start = K0BASE; in rt_hw_cache_init()
202 start = K0BASE; in rt_hw_cache_init()
204 while(start < end) in rt_hw_cache_init()
210 start = K0BASE; in rt_hw_cache_init()
211 while(start < end) in rt_hw_cache_init()
217 start = K0BASE; in rt_hw_cache_init()
[all …]
/libcpu/risc-v/t-head/c908/
A Dcache.c29 static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
30 static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))…
31 static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"…
32 static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))…
37 rt_ubase_t i = start & ~(L1_CACHE_BYTES - 1); \
45 static void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument
50 static void dcachel1_wb_range(unsigned long start, unsigned long end) in dcachel1_wb_range() argument
55 static void dcache_inv_range(unsigned long start, unsigned long end) in dcache_inv_range() argument
60 static void dcache_wbinv_range(unsigned long start, unsigned long end) in dcache_wbinv_range() argument
65 static void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
/libcpu/aarch64/common/include/
A Dtlb.h67 static inline void rt_hw_tlb_invalidate_page(rt_aspace_t aspace, void *start) in rt_hw_tlb_invalidate_page() argument
69 start = TLBI_ARG(start, 0); in rt_hw_tlb_invalidate_page()
74 "isb\n" ::"r"(start) in rt_hw_tlb_invalidate_page()
78 static inline void rt_hw_tlb_invalidate_range(rt_aspace_t aspace, void *start, in rt_hw_tlb_invalidate_range() argument
83 rt_hw_tlb_invalidate_page(aspace, start); in rt_hw_tlb_invalidate_range()
/libcpu/risc-v/t-head/c906/
A Dcache.c29 static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0")));
30 static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))…
31 static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"…
32 static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))…
37 register rt_ubase_t i = start & ~(L1_CACHE_BYTES - 1); \
45 static void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument
50 static void dcache_inv_range(unsigned long start, unsigned long end) in dcache_inv_range() argument
55 static void dcache_wbinv_range(unsigned long start, unsigned long end) in dcache_wbinv_range() argument
60 static void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
/libcpu/sim/posix/
A Dstartup.c7 static int start(void) in start() function
12 __attribute__((section(".init_array"))) typeof(start) *__init = start;
/libcpu/mips/common/
A Dmips_cache.h178 rt_ubase_t start = KSEG0BASE; in blast_dcache16() local
179 rt_ubase_t end = start + g_mips_core.dcache_size; in blast_dcache16()
182 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in blast_dcache16()
188 rt_ubase_t start = KSEG0BASE; in inv_dcache16() local
189 rt_ubase_t end = start + g_mips_core.dcache_size; in inv_dcache16()
192 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in inv_dcache16()
198 rt_ubase_t start = KSEG0BASE; in blast_icache16() local
199 rt_ubase_t end = start + g_mips_core.icache_size; in blast_icache16()
202 for (addr = start; addr < end; addr += g_mips_core.icache_line_size) in blast_icache16()
A Dmips_cache.c112 #define dma_cache_wback_inv(start,size) \ argument
113 do { (void) (start); (void) (size); } while (0)
114 #define dma_cache_wback(start,size) \ argument
115 do { (void) (start); (void) (size); } while (0)
116 #define dma_cache_inv(start,size) \ argument
117 do { (void) (start); (void) (size); } while (0)
/libcpu/risc-v/common64/
A Dtlb.h42 static inline void rt_hw_tlb_invalidate_page(rt_aspace_t aspace, void *start) in rt_hw_tlb_invalidate_page() argument
44 __asm__ volatile("sfence.vma %0, zero" ::"r"(start) : "memory"); in rt_hw_tlb_invalidate_page()
47 static inline void rt_hw_tlb_invalidate_range(rt_aspace_t aspace, void *start, in rt_hw_tlb_invalidate_range() argument
53 rt_hw_tlb_invalidate_page(aspace, start); in rt_hw_tlb_invalidate_range()
A Dsbi.c167 unsigned long start, unsigned long size) in sbi_remote_sfence_vma() argument
175 hart_mask_base, start, size); in sbi_remote_sfence_vma()
179 (void)SBI_CALL3(SBI_REMOTE_SFENCE_VMA, 0, (uint64_t)hart_mask, start, in sbi_remote_sfence_vma()
186 unsigned long start, unsigned long size, in sbi_remote_sfence_vma_asid() argument
195 *hart_mask, 0, start, size, asid); in sbi_remote_sfence_vma_asid()
201 start, size, asid); in sbi_remote_sfence_vma_asid()
A Dsbi.h190 unsigned long start, unsigned long size);
191 void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask, unsigned long start,
/libcpu/ppc/ppc405/
A Dcache.h7 void flush_dcache_range(unsigned long start, unsigned long stop);
8 void clean_dcache_range(unsigned long start, unsigned long stop);
9 void invalidate_dcache_range(unsigned long start, unsigned long stop);
/libcpu/arm/cortex-r52/
A Dbacktrace.c92 const struct unwind_idx *start, in search_index() argument
105 if (addr < (unsigned long)start) in search_index()
110 start = origin; in search_index()
115 while (start < stop - 1) in search_index()
117 const struct unwind_idx *mid = start + ((stop - start) >> 1); in search_index()
130 (unsigned long)start); in search_index()
131 start = mid; in search_index()
136 return start; in search_index()
148 while (start < stop) in unwind_find_origin()
150 const struct unwind_idx *mid = start + ((stop - start) >> 1); in unwind_find_origin()
[all …]
A Dbacktrace.h23 const struct unwind_idx *start; member
A Dstart_iar.S47 ; Define stack start and top
51 ; Align stack start to a 4-byte boundary (32-bit word)
/libcpu/arm/cortex-a/
A Dbacktrace.c91 const struct unwind_idx *start, in search_index() argument
104 if (addr < (unsigned long)start) in search_index()
109 start = origin; in search_index()
114 while (start < stop - 1) in search_index()
116 const struct unwind_idx *mid = start + ((stop - start) >> 1); in search_index()
129 (unsigned long)start); in search_index()
130 start = mid; in search_index()
135 return start; in search_index()
147 while (start < stop) in unwind_find_origin()
149 const struct unwind_idx *mid = start + ((stop - start) >> 1); in unwind_find_origin()
[all …]
A Dtlb.h42 static inline void rt_hw_tlb_invalidate_range(rt_aspace_t aspace, void *start, in rt_hw_tlb_invalidate_range() argument
A Dbacktrace.h24 const struct unwind_idx *start; member
/libcpu/aarch64/common/
A Dcache_ops.c15 void __asm_flush_dcache_range(rt_size_t start, rt_size_t end);
16 void __asm_invalidate_dcache_range(rt_size_t start, rt_size_t end);
17 void __asm_invalidate_icache_range(rt_size_t start, rt_size_t end);
A Dsetup.c125 volatile rt_base_t start = cpu_get_cycles(), cycles; in cpu_us_delay() local
129 while ((cpu_get_cycles() - start) < cycles) in cpu_us_delay()
230 platform_mem_region.start = kernel_start; in rt_hw_common_setup()
253 init_page_region.start = init_page_start - pv_off; in rt_hw_common_setup()
258 platform_mem_region.start = RT_ALIGN_DOWN(platform_mem_region.start, ARCH_PAGE_SIZE); in rt_hw_common_setup()
261 platform_mem_desc.paddr_start = platform_mem_region.start; in rt_hw_common_setup()
262 platform_mem_desc.vaddr_start = platform_mem_region.start - pv_off; in rt_hw_common_setup()
/libcpu/arm/cortex-m7/
A Dmpu.c39 if ((rt_uint32_t)region->start >= 0xE0000000U) in rt_hw_mpu_region_default_attr()
41 …attr = ((rt_uint32_t)region->start >= 0xE0100000U) ? STRONGLY_ORDERED_SHAREABLE : DEVICE_SHAREABLE; in rt_hw_mpu_region_default_attr()
45 attr = default_mem_attr[((rt_uint32_t)region->start & ~0xFFFFFFFU) >> 29U]; in rt_hw_mpu_region_default_attr()
79 if ((rt_uint32_t)region->start & (region->size - 1U) != 0U) in rt_hw_mpu_region_valid()
126 …ARM_MPU_SetRegion(ARM_MPU_RBAR(index, (rt_uint32_t)static_regions[index].start), static_regions[in… in rt_hw_mpu_init()
159 ARM_MPU_SetRegion(ARM_MPU_RBAR(index, (rt_uint32_t)region->start), region->attr.rasr); in rt_hw_mpu_add_region()
206 ARM_MPU_SetRegion(ARM_MPU_RBAR(index, (rt_uint32_t)region->start), region->attr.rasr); in rt_hw_mpu_update_region()
229 …MPU_RBAR(index, (rt_uint32_t)(((rt_mem_region_t *)thread->mem_regions)[i].start)), ((rt_mem_region… in rt_hw_mpu_table_switch()
238 …ARM_MPU_SetRegion(ARM_MPU_RBAR(index, (rt_uint32_t)(exclusive_regions[i].region.start)), exclusive… in rt_hw_mpu_table_switch()
A Dcpuport.c189 stack_top_region.start = (void *)stack_top_region_start; in rt_hw_stack_guard_init()
192 stack_bottom_region.start = (void *)stack_bottom_region_start; in rt_hw_stack_guard_init()
/libcpu/arm/cortex-m33/
A Dmpu.c40 if ((rt_uint32_t)region->start >= 0xE0000000U) in rt_hw_mpu_region_default_attr()
42 …attr = ((rt_uint32_t)region->start >= 0xE0100000U) ? ARM_MPU_ATTR_DEVICE_nGnRE : ARM_MPU_ATTR_DEVI… in rt_hw_mpu_region_default_attr()
46 attr = default_mem_attr[((rt_uint32_t)region->start & ~0xFFFFFFFU) >> 29U]; in rt_hw_mpu_region_default_attr()
57 region->attr.rbar = (rt_uint32_t)region->start | (region->attr.rbar & (~MPU_RBAR_BASE_Msk)); in _mpu_rbar_rlar()
58 rlar |= ((rt_uint32_t)region->start + region->size - 1U) & MPU_RLAR_LIMIT_Msk; in _mpu_rbar_rlar()
116 if ((rt_uint32_t)region->start & (MPU_MIN_REGION_SIZE - 1U) != 0U) in rt_hw_mpu_region_valid()
A Dcpuport.c247 stack_top_region.start = (void *)stack_top_region_start; in rt_hw_stack_guard_init()
250 stack_bottom_region.start = (void *)stack_bottom_region_start; in rt_hw_stack_guard_init()
/libcpu/
A DKconfig116 hex "The virtural address of kernel start"
/libcpu/arm/lpc214x/
A Dstartup_gcc.S18 .global start

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