Searched refs:state (Results 1 – 15 of 15) sorted by relevance
| /libcpu/aarch64/common/include/ |
| A D | psci.h | 106 #define PSCI_POWER_LEVEL_VAL(state) (((state) >> PSCI_POWER_LEVEL_SHIFT) & 0x3) argument
107 #define PSCI_POWER_STATE_TYPE_VAL(state) (((state) >> PSCI_POWER_STATE_TYPE_SHIFT) & 0x1) argument
108 #define PSCI_POWER_STATE_ID_VAL(state) (((state) >> PSCI_POWER_STATE_ID_SHIFT) & 0xffff) argument
145 rt_uint32_t rt_psci_cpu_off(rt_uint32_t state);
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| /libcpu/aarch64/common/ |
| A D | cpu_psci.c | 28 rt_uint32_t state, state_id = PSCI_POWER_STATE_ID(0, 0, 0, PSCI_POWER_STATE_ID_POWERDOWN); in psci_cpu_shutdown() local
30 state = PSCI_POWER_STATE(PSCI_POWER_STATE_LEVEL_CORES, PSCI_POWER_STATE_TYPE_STANDBY, state_id); in psci_cpu_shutdown()
32 rt_psci_cpu_off(state); in psci_cpu_shutdown()
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| A D | psci.c | 30 rt_uint32_t (*cpu_off)(rt_uint32_t state);
124 static rt_uint32_t psci_cpu_off(rt_uint32_t func_id, rt_uint32_t state) in psci_cpu_off() argument
126 return (rt_uint32_t)psci_call(func_id, state, 0, 0); in psci_cpu_off()
129 static rt_uint32_t psci_0_1_cpu_off(rt_uint32_t state) in psci_0_1_cpu_off() argument
131 return psci_cpu_off(psci_0_1_func_ids.cpu_off, state); in psci_0_1_cpu_off()
134 static rt_uint32_t psci_0_2_cpu_off(rt_uint32_t state) in psci_0_2_cpu_off() argument
136 return psci_cpu_off(PSCI_0_2_FN_CPU_OFF, state); in psci_0_2_cpu_off()
242 rt_uint32_t rt_psci_cpu_off(rt_uint32_t state) in rt_psci_cpu_off() argument
244 return PSCI_CALL_FN_RET(cpu_off, state); in rt_psci_cpu_off()
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| /libcpu/arm/cortex-m33/ |
| A D | context_iar.S | 22 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
104 PUSH {r2} ; store interrupt state
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| A D | context_rvds.S | 21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
107 PUSH {r2} ; store interrupt state
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| /libcpu/arm/cortex-m3/ |
| A D | context_iar.S | 20 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| A D | context_rvds.S | 19 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| /libcpu/arm/cortex-m0/ |
| A D | context_iar.S | 20 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| A D | context_rvds.S | 20 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| /libcpu/arm/cortex-m23/ |
| A D | context_iar.S | 21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| A D | context_rvds.S | 21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| /libcpu/arm/cortex-m7/ |
| A D | context_iar.S | 22 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| A D | context_rvds.S | 21 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| /libcpu/arm/cortex-m4/ |
| A D | context_iar.S | 23 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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| A D | context_rvds.S | 22 NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register
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