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/libcpu/aarch64/common/include/
A Dcpuport.h48 #define rt_hw_sysreg_write(sysreg, val) \ argument
49 __asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
51 #define rt_hw_sysreg_read(sysreg, val) \ argument
52 __asm__ volatile ("mrs %0, "RT_STRINGIFY(sysreg)"":"=r"((val)))

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