| /libcpu/risc-v/common64/ |
| A D | interrupt_gcc.S | 45 csrr t0, scause
55 mv a0, t0
70 LOAD a0, 0(t0)
71 la t0, rt_interrupt_to_thread
72 LOAD a1, 0(t0)
73 csrr t0, sstatus
74 andi t0, t0, ~SSTATUS_SPIE
75 csrw sstatus, t0
80 LOAD t0, FRAME_OFF_SSTATUS(sp)
81 andi t0, t0, SSTATUS_SPP
[all …]
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| A D | startup_gcc.S | 42 la t0, trap_entry
43 csrw stvec, t0
79 csrc sstatus, t0
80 li t0, SSTATUS_SUM
81 csrs sstatus, t0
90 li t0, __STACKSIZE__
91 add sp, sp, t0
114 li t0, __STACKSIZE__
115 add sp, sp, t0
121 la t0, trap_entry
[all …]
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| A D | stackframe.h | 117 csrr t0, sscratch
126 csrs sstatus, t0
161 csrc sstatus, t0
165 csrs sstatus, t0
171 andi t0, t0, SSTATUS_VS
172 beqz t0, 0f
192 andi t0, t0, SSTATUS_VS_CLEAN
193 beqz t0, 0f
207 csrs sstatus, t0
242 csrc sstatus, t0
[all …]
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| A D | cpuport_gcc.S | 19 LOAD t0, REGBYTES(sp) /* tentry */
22 jalr t0
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| A D | stack.h | 33 rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ member
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| A D | trap.c | 42 rt_kprintf("\tt0(x5) = %p\tt1(x6) = %p\n", regs->t0, regs->t1); in dump_regs()
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| /libcpu/mips/pic32/ |
| A D | context_gcc.S | 78 la t0, rt_thread_switch_interrupt_flag
79 lw t1, 0(t0)
84 sw t1, 0(t0)
86 sw a0, 0(t0)
89 sw a1, 0(t0)
92 mfc0 t0, CP0_CAUSE /* t0 = Cause */
93 ori t0, t0, (1<<8) /* t0 |= (1<<8) */
94 mtc0 t0, CP0_CAUSE /* cause = t0 */
96 and t0, t0, t1 /* t0 &= t1 */
114 la t0, IFS0CLR /* t0 = IFS0CLR */
[all …]
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| /libcpu/risc-v/vector/rvv-1.0/ |
| A D | rvv_context.h | 53 csrr t0, vstart
55 csrr t0, vtype
57 csrr t0, vl
58 STORE t0, VEC_FRAME_VL(t1)
59 csrr t0, vcsr
60 STORE t0, VEC_FRAME_VCSR(t1)
85 mv t0, \dst
86 addi t1, t0, VEC_FRAME_V0
98 mv t1, t0
101 csrw vstart, t0
[all …]
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| /libcpu/mips/common/ |
| A D | entry_gcc.S | 39 dli t0, ST0_KX
40 MTC0 t0, CP0_STATUS
51 PTR_LA t0, __bss_start
55 sw zero, 0(t0)
56 bne t1, t0, _clr_bss_loop
57 addu t0, 4
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| A D | context_gcc.S | 54 PTR_LA t0, rt_thread_switch_interrupt_flag
55 REG_L t1, 0(t0)
60 LONG_S t1, 0(t0)
61 PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
62 LONG_S a0, 0(t0)
64 PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
65 LONG_S a1, 0(t0)
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| A D | mips.inc | 22 #define t0 $8 /* caller saved */
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| A D | mips_regs.h | 29 #define t0 $8 /* caller saved */ macro
78 #define t0 $12 /* caller saved */ macro
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| /libcpu/mips/gs264/ |
| A D | cpuinit_gcc.S | 22 mfc0 t0, CP0_CONFIG
23 ori t0, 3
24 mtc0 t0, CP0_CONFIG
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| /libcpu/mips/gs232/ |
| A D | cache_gcc.S | 71 la t0, memvar
72 sw t7, 0x0(t0) #ways
73 sw t5, 0x4(t0) #icache size
142 mfc0 t0, CP0_CONFIG
144 and t0, ~0x03
145 or t0, 0x03
146 mtc0 t0, CP0_CONFIG
158 mfc0 t0, CP0_CONFIG
160 and t0, ~0x03
161 or t0, 0x2
[all …]
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| /libcpu/risc-v/common/ |
| A D | interrupt_gcc.S | 69 li t0, 0x80
70 STORE t0, 2 * REGBYTES(sp)
113 lw t2, 0(t0)
116 sw zero, 0(t0)
122 LOAD t1, 0(t0)
126 LOAD t1, 0(t0)
136 li t0, 0x1800
137 csrs mstatus, t0
139 csrs mstatus, t0
308 csrr t0, mhartid
[all …]
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| A D | context_gcc.S | 50 la t0, __rt_rvstack
61 addi t0, t0, -512 // for ch32
63 csrw mscratch,t0
221 csrr t0, mhartid
224 addi t1, t0, 1
239 li t0, 0x7800
241 li t0, 0x1800
243 csrw mstatus, t0
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| A D | readme.md | 83 la t0, SW_handler
84 csrw mtvec, t0
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| A D | rt_hw_stack_frame.h | 23 rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ member
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| A D | trap_common.c | 93 rt_kprintf("t0 : 0x%08x\r\n", s_stack_frame->t0); in rt_show_stack_frame()
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