Searched refs:t1 (Results 1 – 17 of 17) sorted by relevance
| /libcpu/risc-v/vector/rvv-1.0/ |
| A D | rvv_context.h | 51 mv t1, \dst
62 addi t1, t1, VEC_FRAME_V0
68 vse8.v v0, (t1)
69 add t1, t1, t2
70 vse8.v v8, (t1)
71 add t1, t1, t2
73 add t1, t1, t2
91 add t1, t1, t2
93 add t1, t1, t2
95 add t1, t1, t2
[all …]
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| /libcpu/risc-v/common64/ |
| A D | stackframe.h | 122 mv t1, sp
123 addi t1, t1, CTX_GENERAL_REG_NR * REGBYTES
127 FSTORE f0, FPU_CTX_F0_OFF(t1)
128 FSTORE f1, FPU_CTX_F1_OFF(t1)
129 FSTORE f2, FPU_CTX_F2_OFF(t1)
130 FSTORE f3, FPU_CTX_F3_OFF(t1)
131 FSTORE f4, FPU_CTX_F4_OFF(t1)
132 FSTORE f5, FPU_CTX_F5_OFF(t1)
133 FSTORE f6, FPU_CTX_F6_OFF(t1)
177 SAVE_VECTOR t1
[all …]
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| A D | interrupt_gcc.S | 48 li t1, 8
49 bne t0, t1, _handle_interrupt_and_exception
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| A D | startup_gcc.S | 35 mv t1, a0 /* get hartid in S-mode frome a0 register */
36 …sw t1, (t0) /* store t1 register low 4 bits in memory address which is store…
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| A D | stack.h | 34 rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ member
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| A D | trap.c | 42 rt_kprintf("\tt0(x5) = %p\tt1(x6) = %p\n", regs->t0, regs->t1); in dump_regs()
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| /libcpu/mips/pic32/ |
| A D | context_gcc.S | 79 lw t1, 0(t0)
81 bnez t1, _reswitch
83 li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
84 sw t1, 0(t0)
95 addiu t1, zero, -257 /* t1 = ~(1<<8) */
96 and t0, t0, t1 /* t0 &= t1 */
115 addiu t1,zero,0x02 /* t1 = (1<<2) */
116 sw t1, 0(t0) /* IFS0CLR = t1 */
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| /libcpu/mips/common/ |
| A D | context_gcc.S | 55 REG_L t1, 0(t0)
57 bnez t1, _reswitch
59 li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
60 LONG_S t1, 0(t0)
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| A D | entry_gcc.S | 52 PTR_LA t1, __bss_end
56 bne t1, t0, _clr_bss_loop
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| A D | stackframe.h | 25 lui t1, %hi(ST0_CU1)
26 addiu t1, t1, %lo(ST0_CU1)
27 or v1, v1, t1
130 lui t1, %hi(ST0_CU1)
131 addiu t1, t1, %lo(ST0_CU1)
132 or v1, v1, t1
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| A D | mips.inc | 23 #define t1 $9
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| A D | mips_regs.h | 30 #define t1 $9 macro
79 #define t1 $13 macro
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| /libcpu/risc-v/common/ |
| A D | interrupt_gcc.S | 122 LOAD t1, 0(t0)
123 STORE sp, 0(t1)
126 LOAD t1, 0(t0)
127 LOAD sp, 0(t1)
312 addi t1, t0, 1
314 mul t1, t1, t2
315 add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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| A D | context_gcc.S | 224 addi t1, t0, 1
226 mul t1, t1, t2
227 add sp, sp, t1 /* sp = (cpuid + 1) * __STACKSIZE__ + __stack_start__ */
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| A D | rt_hw_stack_frame.h | 24 rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ member
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| A D | trap_common.c | 94 rt_kprintf("t1 : 0x%08x\r\n", s_stack_frame->t1); in rt_show_stack_frame()
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| /libcpu/mips/gs232/ |
| A D | cache_gcc.S | 26 move t1,ra
131 jr t1
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