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/libcpu/blackfin/bf53x/
A Dcpuport.c59 void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch() argument
67 rt_interrupt_to_thread = to; in rt_hw_context_switch()
71 void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch_interrupt() argument
79 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
83 void rt_hw_context_switch_to(rt_uint32_t to) in rt_hw_context_switch_to() argument
87 rt_interrupt_to_thread = to; in rt_hw_context_switch_to()
/libcpu/arm/cortex-m4/
A DREADME.md4 …he operating system. The independent interrupt management module is designed to solve this problem.
6 The independent interrupt management module is designed to solve the problem of interrupt delays ca…
10 - Add the following code to the project's `board.c` file.
33 - Add the following configuration to the `Kconfig` file in the `board` directory.
46 - Select `RT_USING_INDEPENDENT_INTERRUPT_MANAGEMENT` to enable this feature.
47 - Select `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` to set the maximum priority of the interrupt that can …
50 …registers-for-exception-masking/BASEPRI) register is used in the functions to complete the interru…
51 - For example, if `RT_MAX_SYSCALL_INTERRUPT_PRIORITY` is set to 0x01, the system masking only inter…
52 - Interrupts with a priority of 0 are not managed by the system and can continue to respond to inte…
A Dcontext_rvds.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
65 ; set rt_thread_switch_interrupt_flag to 1
87 ; r1 --> switch to thread stack
92 ; disable interrupt to protect context switch
101 ; clear rt_thread_switch_interrupt_flag to 0
169 ; set to thread
180 ; set from thread to 0
185 ; set interrupt flag to 1
212 ; clear the BASEPRI register to disable masking priority
258 MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP.
[all …]
A Dcontext_iar.S26 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
65 ; set rt_thread_switch_interrupt_flag to 1
86 ; r1 --> switch to thread stack
91 ; disable interrupt to protect context switch
100 ; clear rt_thread_switch_interrupt_flag to 0
182 ; set from thread to 0
187 ; set interrupt flag to 1
214 ; clear the BASEPRI register to disable masking priority
265 MSR psp, r0 ; update stack pointer to PSP.
268 MSR msp, r0 ; update stack pointer to MSP.
/libcpu/ti-dsp/c28x/
A Dcontext.s102 ; void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
104 ; SP[4] --> to
113 ; note this convention is only applicable to normal functions not to isrs
117 ; set rt_thread_switch_interrupt_flag to 1
136 ; SP[4] --> to
143 ; set rt_thread_switch_interrupt_flag to 1
160 ; * void rt_hw_context_switch_to(rt_uint32 to);
161 ; * ACC --> to
165 ; get to thread
169 ; set from thread to 0
[all …]
/libcpu/arm/cortex-m0/
A Dcontext_iar.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
60 ; set rt_thread_switch_interrupt_flag to 1
81 ; r1 --> switch to thread stack
86 ; disable interrupt to protect context switch
96 ; clear rt_thread_switch_interrupt_flag to 0
113 MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
125 PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
128 MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
152 ; set to thread
156 ; set from thread to 0
[all …]
A Dcontext_rvds.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
63 ; set rt_thread_switch_interrupt_flag to 1
85 ; r1 --> switch to thread stack
90 ; disable interrupt to protect context switch
100 ; clear rt_thread_switch_interrupt_flag to 0
117 MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
129 PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
132 MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
157 ; set to thread
161 ; set from thread to 0
[all …]
/libcpu/arm/cortex-m23/
A Dcontext_iar.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
61 ; set rt_thread_switch_interrupt_flag to 1
82 ; r1 --> switch to thread stack
87 ; disable interrupt to protect context switch
97 ; clear rt_thread_switch_interrupt_flag to 0
114 MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
126 PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
129 MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
153 ; set to thread
157 ; set from thread to 0
[all …]
A Dcontext_rvds.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
64 ; set rt_thread_switch_interrupt_flag to 1
86 ; r1 --> switch to thread stack
91 ; disable interrupt to protect context switch
101 ; clear rt_thread_switch_interrupt_flag to 0
118 MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7}
130 PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11}
133 MOV r8, r4 ; mov {r4 - r7} to {r8 - r11}
158 ; set to thread
162 ; set from thread to 0
[all …]
/libcpu/m16c/m16c62p/
A Dcpuport.c77 void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch() argument
80 rt_interrupt_to_thread = to; in rt_hw_context_switch()
84 void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch_interrupt() argument
91 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
/libcpu/v850/70f34/
A Dcpuport.c81 void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch() argument
84 rt_interrupt_to_thread = to; in rt_hw_context_switch()
88 void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch_interrupt() argument
95 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
/libcpu/rx/
A Dcpuport.c146 void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch() argument
154 rt_interrupt_to_thread = to; in rt_hw_context_switch()
165 void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) in rt_hw_context_switch_interrupt() argument
173 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
184 void rt_hw_context_switch_to(rt_uint32_t to) in rt_hw_context_switch_to() argument
188 rt_interrupt_to_thread = to; in rt_hw_context_switch_to()
/libcpu/arm/cortex-m33/
A Dsyscall_rvds.S30 MOV R4, R1 ; copy thread SP to R4
36 BX LR ; return to thread
41 BX LR ; return to user app
51 ; get SP, save to R1
A Dcontext_rvds.S67 ; set rt_thread_switch_interrupt_flag to 1
89 ; r1 --> switch to thread stack
94 ; disable interrupt to protect context switch
109 ; clear rt_thread_switch_interrupt_flag to 0
134 ; push PSPLIM CONTROL PSP LR current_context to stack
138 STMFD r5!, {r1-r4} ; push to thread stack
214 ; set to thread
225 ; set from thread to 0
230 ; set interrupt flag to 1
299 MSR psp, r0 ; update stack pointer to PSP
[all …]
A Dcontext_iar.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
65 ; set rt_thread_switch_interrupt_flag to 1
86 ; r1 --> switch to thread stack
91 ; disable interrupt to protect context switch
106 ; clear rt_thread_switch_interrupt_flag to 0
131 ; push PSPLIM CONTROL PSP LR current_context to stack
135 STMFD r5!, {r1-r4} ; push to thread stack
160 STMFD r1!, {r2-r5} ; push to thread stack
224 ; set from thread to 0
229 ; set interrupt flag to 1
[all …]
/libcpu/arm/cortex-m3/
A Dcontext_rvds.S22 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
62 ; set rt_thread_switch_interrupt_flag to 1
84 ; r1 --> switch to thread stack
89 ; disable interrupt to protect context switch
98 ; clear rt_thread_switch_interrupt_flag to 0
134 ; set to thread
138 ; set from thread to 0
143 ; set interrupt flag to 1
198 MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP.
199 MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP.
A Dcontext_iar.S23 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
60 ; set rt_thread_switch_interrupt_flag to 1
81 ; r1 --> switch to thread stack
86 ; disable interrupt to protect context switch
95 ; clear rt_thread_switch_interrupt_flag to 0
132 ; set from thread to 0
137 ; set interrupt flag to 1
193 MSR psp, r0 ; update stack pointer to PSP.
196 MSR msp, r0 ; update stack pointer to MSP.
/libcpu/arm/cortex-m7/
A Dcontext_rvds.S24 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
64 ; set rt_thread_switch_interrupt_flag to 1
86 ; r1 --> switch to thread stack
91 ; disable interrupt to protect context switch
100 ; clear rt_thread_switch_interrupt_flag to 0
168 ; set to thread
179 ; set from thread to 0
184 ; set interrupt flag to 1
244 MSREQ msp, r0 ; [2]=0 ==> Z=1, update stack pointer to MSP.
245 MSRNE psp, r0 ; [2]=1 ==> Z=0, update stack pointer to PSP.
A Dcontext_iar.S25 NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception
62 ; set rt_thread_switch_interrupt_flag to 1
83 ; r1 --> switch to thread stack
88 ; disable interrupt to protect context switch
97 ; clear rt_thread_switch_interrupt_flag to 0
179 ; set from thread to 0
184 ; set interrupt flag to 1
244 MSR psp, r0 ; update stack pointer to PSP.
247 MSR msp, r0 ; update stack pointer to MSP.
/libcpu/arc/em/
A Dcpuport.c66 void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to) in set_hw_stack_check() argument
69 if (to != NULL) { in set_hw_stack_check()
70 rt_thread_to = rt_container_of(to, struct rt_thread, sp); in set_hw_stack_check()
/libcpu/arm/sep4020/
A Dstart_rvds.S97 ; Mapped to Address 0.
175 MOV R4, #0xD2 ;chmod to irq and init SP_irq
179 MOV R4, #0XD1 ;chomod to fiq and init SP_fiq
183 MOV R4, #0XD7 ;chomod to abt and init SP_ABT
187 MOV R4, #0XDB ;chomod to undf and init SP_UNDF
191 ;chomod to abt and init SP_sys
250 ; Copy Exception Vectors to Internal RAM
263 ; Remap on-chip RAM to address 0
282 BIC R4, R4, #0x80 ; set bit7 to zero
305 ; if rt_thread_switch_interrupt_flag set, jump to
[all …]
/libcpu/ia32/
A Dcpuport.c31 void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thr… in rt_hw_context_switch_interrupt() argument
36 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
/libcpu/risc-v/common/
A Dcpuport.c87 rt_weak void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread… in rt_hw_context_switch_interrupt() argument
92 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
/libcpu/risc-v/common64/
A Dcpuport.c110 void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thr… in rt_hw_context_switch_interrupt() argument
115 rt_interrupt_to_thread = to; in rt_hw_context_switch_interrupt()
/libcpu/arm/realview-a8-vmm/
A Dstart_gcc.S148 @ if rt_thread_switch_interrupt_flag set, jump to
166 sub r2, lr, #4 @ save old task's pc to r2
168 @ Switch to SVC mode with no interrupt. If the usr mode guest is
169 @ interrupted, this will just switch to the stack of kernel space.
187 ldmfd sp!, {r4} @ pop new task's cpsr to spsr

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