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Searched refs:uic0msr (Results 1 – 2 of 2) sorted by relevance

/libcpu/ppc/ppc405/include/asm/
A Dppc4xx-uic.h30 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ macro
40 #define uicmsr uic0msr
/libcpu/ppc/ppc405/
A Dtraps.c119 uic_msr = mfdcr(uic0msr); in external_interrupt()

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