| /libcpu/risc-v/common64/ |
| A D | riscv_io.h | 88 #define writeb_relaxed(v,c) ({ __io_rbw(); __raw_writeb((v),(c)); __io_raw(); }) argument
89 #define writew_relaxed(v,c) ({ __io_rbw(); __raw_writew((v),(c)); __io_raw(); }) argument
90 #define writel_relaxed(v,c) ({ __io_rbw(); __raw_writel((v),(c)); __io_raw(); }) argument
94 #define writeq_relaxed(v,c) ({ __io_rbw(); __raw_writeq((v),(c)); __io_raw(); }) argument
106 #define writeb(v,c) ({ __io_bw(); __raw_writeb((v),(c)); __io_aw(); }) argument
107 #define writew(v,c) ({ __io_bw(); __raw_writew((v),(c)); __io_aw(); }) argument
108 #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); }) argument
112 #define writeq(v,c) ({ __io_bw(); __raw_writeq((v),(c)); __io_aw(); }) argument
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| A D | io.h | 19 #define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) argument
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| A D | README.md | 44 创建`libcpu/risc-v/<VENDOR_NAME>/<CPU_NAME>`新目录，同时在`libcpu/risc-v/SConscript`中增加该CPU。
48 `libcpu/risc-v/virt64/plic.[c|h]`提供了符合《RISC-V Platform-Level Interrupt Controller Specification ver…
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| A D | stack.h | 66 rt_ubase_t v[CTX_VECTOR_REG_NR]; member
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| A D | mmu.c | 421 size_t v = vtable[l1_off]; in rt_hw_mmu_map_init() local
423 if (v) in rt_hw_mmu_map_init()
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| /libcpu/arm/zynqmp-r5/ |
| A D | xpseudo_asm_gcc.h | 72 #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) argument
82 #define mtgpr(rn, v) /*__asm__ __volatile__(\ argument
121 #define mtelrel3(v) __asm__ __volatile__ ("msr ELR_EL3, %0" : : "r" (v)) argument
134 #define mtcpsr(v) __asm__ __volatile__(\
136 : : "r" (v)\
147 #define mtgpr(rn, v) __asm__ __volatile__(\
149 : : "r" (v)\
227 #define mtcp(rn, v) __asm__ __volatile__(\
229 : : "r" (v)\
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| /libcpu/risc-v/vector/rvv-1.0/ |
| A D | rvv_context.h | 68 vse8.v v0, (t1)
70 vse8.v v8, (t1)
72 vse8.v v16, (t1)
74 vse8.v v24, (t1)
90 vle8.v v0, (t1)
92 vle8.v v8, (t1)
94 vle8.v v16, (t1)
96 vle8.v v24, (t1)
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| /libcpu/arm/cortex-a/ |
| A D | trap.c | 110 uint32_t v; in rt_hw_show_register() local
111 asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(v)); in rt_hw_show_register()
112 rt_kprintf("dfsr:0x%08x\n", v); in rt_hw_show_register()
113 asm volatile ("MRC p15, 0, %0, c2, c0, 0":"=r"(v)); in rt_hw_show_register()
114 rt_kprintf("ttbr0:0x%08x\n", v); in rt_hw_show_register()
115 asm volatile ("MRC p15, 0, %0, c6, c0, 0":"=r"(v)); in rt_hw_show_register()
116 rt_kprintf("dfar:0x%08x\n", v); in rt_hw_show_register()
117 rt_kprintf("0x%08x -> 0x%08x\n", v, rt_kmem_v2p((void *)v)); in rt_hw_show_register()
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| A D | tlb.h | 22 #define WRITE_CP32(v, name...) do { \ argument
23 register uint32_t _r = (v); \
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| A D | mmu.c | 198 size_t v = vtable[l1_off]; in rt_hw_mmu_map_init() local
200 if (v & ARCH_MMU_USED_MASK) in rt_hw_mmu_map_init()
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| /libcpu/risc-v/common/ |
| A D | readme.md | 95 - 示例（core-v-mcu链接脚本）：
109 > __stack_top为core-v-mcu工程的中断栈顶名 不同工程此处的名称可能不一致 按上述方法将给出的代码放到具体工程链接脚本中断栈顶名称之后即可。
115 方式一：面向非向量中断管理方式(例:core-v-mcu)
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| /libcpu/ppc/ppc405/include/asm/ |
| A D | processor.h | 1030 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) argument
1034 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) argument
1039 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) argument
1041 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) argument
1072 #define CPU_TYPE_ENTRY(n, v) \ argument
1073 { .name = #n, .soc_ver = SVR_##v, }
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| /libcpu/mips/gs264/ |
| A D | mips_mmu.c | 173 entry_lo -> v = 1; in mmu_set_map()
219 …rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_l… in tlb_dump()
220 …rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_l… in tlb_dump()
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| A D | mips_mmu.h | 45 uint64_t v : 1; member
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| A D | mmu.c | 239 size_t v = vtable[l1_off]; in rt_hw_mmu_map_init() local
241 if (v & ARCH_MMU_USED_MASK) in rt_hw_mmu_map_init()
243 … rt_kprintf("Error:vtable[%d] = 0x%p(is not zero),va_s = 0x%p,va_e = 0x%p!\n",l1_off,v,va_s,va_e); in rt_hw_mmu_map_init()
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| /libcpu/ |
| A D | Kconfig | 270 Using the common64 implementation under ./libcpu/risc-v
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