Home
last modified time | relevance | path

Searched refs:val (Results 1 – 25 of 31) sorted by relevance

12

/libcpu/mips/gs232/
A Dmipscfg.c52 rt_uint16_t val; in mips32_cfg_init() local
60 val = (cp0_config1 & (7<<22))>>22; in mips32_cfg_init()
62 val = (cp0_config1 & (7<<19))>>19; in mips32_cfg_init()
64 val = (cp0_config1 & (7<<16))>>16; in mips32_cfg_init()
65 g_mips_core.icache_ways = val + 1; in mips32_cfg_init()
67 val = (cp0_config1 & (7<<13))>>13; in mips32_cfg_init()
69 val = (cp0_config1 & (7<<10))>>10; in mips32_cfg_init()
71 val = (cp0_config1 & (7<<7))>>7; in mips32_cfg_init()
72 g_mips_core.dcache_ways = val + 1; in mips32_cfg_init()
74 val = (cp0_config1 & (0x3F<<25))>>25; in mips32_cfg_init()
[all …]
/libcpu/mips/gs264/
A Dmipscfg.c54 rt_uint16_t val; in mips32_cfg_init() local
62 val = (cp0_config1 & (7<<22))>>22; in mips32_cfg_init()
64 val = (cp0_config1 & (7<<19))>>19; in mips32_cfg_init()
66 val = (cp0_config1 & (7<<16))>>16; in mips32_cfg_init()
67 g_mips_core.icache_ways = val + 1; in mips32_cfg_init()
69 val = (cp0_config1 & (7<<13))>>13; in mips32_cfg_init()
71 val = (cp0_config1 & (7<<10))>>10; in mips32_cfg_init()
73 val = (cp0_config1 & (7<<7))>>7; in mips32_cfg_init()
74 g_mips_core.dcache_ways = val + 1; in mips32_cfg_init()
76 val = (cp0_config1 & (0x3F<<25))>>25; in mips32_cfg_init()
[all …]
A Dmips_mmu.h72 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) argument
/libcpu/mips/common/
A Dmips_regs.h825 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) argument
834 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) argument
843 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) argument
848 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) argument
851 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) argument
863 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) argument
868 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) argument
930 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) argument
933 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) argument
936 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) argument
[all …]
/libcpu/risc-v/common/
A Datomic_riscv.c13 rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_exchange() argument
17 asm volatile ("amoswap.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); in rt_hw_atomic_exchange()
19 asm volatile ("amoswap.d %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); in rt_hw_atomic_exchange()
24 rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_add() argument
28 asm volatile ("amoadd.w %0, %1, (%2)" : "=r"(result) : "r"(val), "r"(ptr) : "memory"); in rt_hw_atomic_add()
35 rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_sub() argument
38 val = -val; in rt_hw_atomic_sub()
47 rt_atomic_t rt_hw_atomic_xor(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_xor() argument
58 rt_atomic_t rt_hw_atomic_and(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_and() argument
69 rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_or() argument
[all …]
A Driscv-ops.h20 #define write_csr(reg, val) ({ \ argument
21 if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
22 asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
24 asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
/libcpu/risc-v/common64/
A Driscv_io.h21 asm volatile("sb %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writeb()
26 asm volatile("sh %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writew()
31 asm volatile("sw %0, 0(%1)" : : "r"(val), "r"(addr)); in __raw_writel()
43 rt_uint8_t val; in __raw_readb() local
46 return val; in __raw_readb()
51 rt_uint16_t val; in __raw_readw() local
54 return val; in __raw_readw()
59 rt_uint32_t val; in __raw_readl() local
62 return val; in __raw_readl()
68 rt_uint64_t val; in __raw_readq() local
[all …]
A Dio.h25 static inline void writel(uint32_t val, volatile void *addr) in writel() argument
28 __arch_putl(val, addr); in writel()
33 uint32_t val; in readl() local
35 val = __arch_getl(addr); in readl()
37 return val; in readl()
41 uint32_t val, volatile void *addr, unsigned offset) in write_reg() argument
43 writel(val, (void *)((rt_size_t)addr + offset)); in write_reg()
A Dsbi.c116 void sbi_set_timer(uint64_t val) in sbi_set_timer() argument
123 ret = SBI_CALL1(SBI_EXT_ID_TIME, SBI_TIME_SET_TIMER, val); in sbi_set_timer()
128 (void)SBI_CALL1(SBI_SET_TIMER, 0, val); in sbi_set_timer()
/libcpu/ppc/ppc405/
A Dio.h24 static inline void out_8(volatile unsigned char __iomem *addr, int val) in out_8() argument
26 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); in out_8()
50 extern inline void out_le16(volatile unsigned short __iomem *addr, int val) in out_le16() argument
53 "r" (val), "r" (addr)); in out_le16()
56 extern inline void out_be16(volatile unsigned short __iomem *addr, int val) in out_be16() argument
58 __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); in out_be16()
82 extern inline void out_le32(volatile unsigned __iomem *addr, int val) in out_le32() argument
85 "r" (val), "r" (addr)); in out_le32()
88 extern inline void out_be32(volatile unsigned __iomem *addr, int val) in out_be32() argument
90 __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); in out_be32()
A Dtraps.c21 rt_inline void set_tsr(unsigned long val) in set_tsr() argument
23 mtspr(SPRN_TSR, val); in set_tsr()
28 rt_uint32_t val; in get_esr() local
30 val = mfspr(SPRN_ESR); in get_esr()
31 return val; in get_esr()
133 unsigned long fixup, val; in MachineCheckException() local
137 val = mfspr(MCSR); in MachineCheckException()
139 mtspr(SPRN_MCSR, val); in MachineCheckException()
147 val = get_esr(); in MachineCheckException()
149 if (val& ESR_IMCP) { in MachineCheckException()
[all …]
A Dserial.c283 volatile rt_uint8_t val; in rt_hw_serial_init() local
303 val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ in rt_hw_serial_init()
304 val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ in rt_hw_serial_init()
/libcpu/arm/sep4020/
A Dclk.c73 rt_uint32_t val; in rt_hw_get_clock() local
77 val =*(RP) PMU_PMCR; in rt_hw_get_clock()
79 npd = (val >> 14) & 0x01; in rt_hw_get_clock()
81 pd = (val >> 10) & 0x0f; in rt_hw_get_clock()
83 pv = val & 0x7f; in rt_hw_get_clock()
86 val = 2 * CLK_IN * pv; in rt_hw_get_clock()
88 val = CLK_IN * pv / (pd + 1); in rt_hw_get_clock()
90 return(val); in rt_hw_get_clock()
/libcpu/arm/s3c24x0/
A Dsystem_clock.c38 rt_uint32_t val; in rt_hw_get_clock() local
41 val = MPLLCON; in rt_hw_get_clock()
42 m = (val>>12)&0xff; in rt_hw_get_clock()
43 p = (val>>4)&0x3f; in rt_hw_get_clock()
44 s = val&3; in rt_hw_get_clock()
48 val = CLKDIVN; in rt_hw_get_clock()
49 m = (val>>1)&3; in rt_hw_get_clock()
50 p = val&1; in rt_hw_get_clock()
/libcpu/arm/common/
A Datomic_arm.c87 void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_store() argument
92 } while ((__STREXW(val, ptr)) != 0U); in rt_hw_atomic_store()
95 rt_atomic_t rt_hw_atomic_add(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_add() argument
101 } while ((__STREXW(oldval + val, ptr)) != 0U); in rt_hw_atomic_add()
105 rt_atomic_t rt_hw_atomic_sub(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_sub() argument
111 } while ((__STREXW(oldval - val, ptr)) != 0U); in rt_hw_atomic_sub()
121 } while ((__STREXW(oldval & val, ptr)) != 0U); in rt_hw_atomic_and()
125 rt_atomic_t rt_hw_atomic_or(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_or() argument
131 } while ((__STREXW(oldval | val, ptr)) != 0U); in rt_hw_atomic_or()
141 } while ((__STREXW(oldval ^ val, ptr)) != 0U); in rt_hw_atomic_xor()
[all …]
/libcpu/arm/zynqmp-r5/
A Dxpseudo_asm_gcc.h191 #define str(adr, val) __asm__ __volatile__(\ argument
193 : : "r" (val), "r" (adr)\
196 #define strb(adr, val) __asm__ __volatile__(\ argument
198 : : "r" (val), "r" (adr)\
211 #define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) argument
212 #define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) argument
216 #define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) argument
223 #define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) argument
/libcpu/ppc/ppc405/include/asm/
A Dppc4xx.h43 #define static_cast(type, val) (type)(val) argument
45 #define static_cast(type, val) (val) argument
118 rt_uint32_t val; in get_mcsr() local
120 asm volatile("mfspr %0, 0x23c" : "=r" (val) :); in get_mcsr()
121 return val; in get_mcsr()
124 static inline void set_mcsr(rt_uint32_t val) in set_mcsr() argument
126 asm volatile("mtspr 0x23c, %0" : "=r" (val) :); in set_mcsr()
/libcpu/aarch64/common/
A Datomic_aarch64.c28 void rt_hw_atomic_store(volatile rt_atomic_t *ptr, rt_atomic_t val) in rt_hw_atomic_store() argument
34 : "r" (val) in rt_hw_atomic_store()
41 rt_atomic_t tmp, val, result; \
50 : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Q" (*ptr) \
63 rt_atomic_t rt_hw_atomic_exchange(volatile rt_atomic_t *ptr, rt_atomic_t val) in AARCH64_ATOMIC_OP_RETURN()
74 : "r" (val) in AARCH64_ATOMIC_OP_RETURN()
A Dcpuport.c64 unsigned long val; in __rt_clz()
67 :"=r"(val) in __rt_clz()
70 return val; in __rt_clz()
/libcpu/aarch64/common/include/
A Dcpuport.h48 #define rt_hw_sysreg_write(sysreg, val) \ argument
49 __asm__ volatile ("msr "RT_STRINGIFY(sysreg)", %0"::"r"((rt_uint64_t)(val)))
51 #define rt_hw_sysreg_read(sysreg, val) \ argument
52 __asm__ volatile ("mrs %0, "RT_STRINGIFY(sysreg)"":"=r"((val)))
/libcpu/arm/cortex-r52/
A Dtrap.c101 uint32_t val; in rt_hw_trap_undef() local
113 asm volatile ("vmrs %0, fpexc" : "=r"(val)::"memory"); in rt_hw_trap_undef()
115 if (!(val & 0x40000000)) in rt_hw_trap_undef()
118 val = (1U << 30); in rt_hw_trap_undef()
120 asm volatile ("vmsr fpexc, %0"::"r"(val):"memory"); in rt_hw_trap_undef()
/libcpu/ti-dsp/c6x/
A Dtrap.h72 extern int __fls(int val);
73 extern int __ffs(int val);
A Dcontext.asm89 ; rt_int32_t __fls(rt_int32_t val)
100 ; rt_int32_t __ffs(rt_int32_t val)
/libcpu/risc-v/virt64/
A Dplic.h75 void plic_set_thresh(rt_uint32_t val);
76 void plic_set_ie(rt_uint32_t word_index,rt_uint32_t val);
A Dplic.c116 void plic_set_ie(rt_uint32_t word_index, rt_uint32_t val) in plic_set_ie() argument
119 writel(val, plic_ie); in plic_set_ie()

Completed in 42 milliseconds

12