Home
last modified time | relevance | path

Searched refs:value (Results 1 – 25 of 63) sorted by relevance

123

/libcpu/aarch64/common/
A Dcpuport.c26 int __rt_ffs(int value) in __rt_ffs() argument
29 return __builtin_ffs(value); in __rt_ffs()
36 : "=r"(value) in __rt_ffs()
37 : "0"(value) in __rt_ffs()
39 return value; in __rt_ffs()
46 return __builtin_ffsl(value); in __rt_ffsl()
48 if (!value) in __rt_ffsl()
55 return __rt_clz(value); in __rt_ffsl()
59 unsigned long __rt_clz(unsigned long value) in __rt_clz() argument
62 return __builtin_clz(value); in __rt_clz()
[all …]
A Dtrap.c178 uint32_t value = 0; in _rt_hw_trap_irq() local
179 value = IRQ_PEND_BASIC & 0x3ff; in _rt_hw_trap_irq()
203 if (value) in _rt_hw_trap_irq()
205 if (value & (1 << 8)) in _rt_hw_trap_irq()
207 value = IRQ_PEND1; in _rt_hw_trap_irq()
208 irq = __rt_ffs(value) - 1; in _rt_hw_trap_irq()
210 else if (value & (1 << 9)) in _rt_hw_trap_irq()
212 value = IRQ_PEND2; in _rt_hw_trap_irq()
213 irq = __rt_ffs(value) + 31; in _rt_hw_trap_irq()
217 value &= 0x0f; in _rt_hw_trap_irq()
[all …]
/libcpu/arm/arm926/
A Dmmu.c24 value = 0; in mmu_setttbase()
43 orr value, value, #0x01 in mmu_enable()
55 bic value, value, #0x01 in mmu_disable()
67 orr value, value, #0x1000 in mmu_enable_icache()
79 orr value, value, #0x04 in mmu_enable_dcache()
91 bic value, value, #0x1000 in mmu_disable_icache()
103 bic value, value, #0x04 in mmu_disable_dcache()
115 orr value, value, #0x02 in mmu_enable_alignfault()
127 bic value, value, #0x02 in mmu_disable_alignfault()
180 value = 0; in mmu_invalidate_tlb()
[all …]
A Dcpuport.c68 rt_uint32_t value; in cache_enable() local
73 orr value, value, bit in cache_enable()
80 rt_uint32_t value; in cache_disable() local
85 bic value, value, bit in cache_disable()
189 int __rt_ffs(int value) in __rt_ffs() argument
193 if (value == 0) in __rt_ffs()
194 return value; in __rt_ffs()
198 rsb x, value, #0 in __rt_ffs()
199 and x, x, value in __rt_ffs()
207 int __rt_ffs(int value) in __rt_ffs() argument
[all …]
/libcpu/arm/dm36x/
A Dcpuport.c67 rt_uint32_t value; in cache_enable() local
72 orr value, value, bit in cache_enable()
79 rt_uint32_t value; in cache_disable() local
84 bic value, value, bit in cache_disable()
192 if (value == 0) in __rt_ffs()
193 return value; in __rt_ffs()
208 if (value == 0) in __rt_ffs()
209 return value; in __rt_ffs()
219 if (value == 0) in __rt_ffs()
222 value &= (-value); in __rt_ffs()
[all …]
A Dmmu.c22 value = 0; in mmu_setttbase()
51 orr value, value, #0x01 in mmu_enable()
63 bic value, value, #0x01 in mmu_disable()
75 orr value, value, #0x1000 in mmu_enable_icache()
87 orr value, value, #0x04 in mmu_enable_dcache()
99 bic value, value, #0x1000 in mmu_disable_icache()
111 bic value, value, #0x04 in mmu_disable_dcache()
123 orr value, value, #0x02 in mmu_enable_alignfault()
135 bic value, value, #0x02 in mmu_disable_alignfault()
200 value = 0; in mmu_invalidate_tlb()
[all …]
/libcpu/arm/armv6/
A Dcpuport.c69 rt_uint32_t value; in cache_enable() local
74 orr value, value, bit in cache_enable()
81 rt_uint32_t value; in cache_disable() local
86 bic value, value, bit in cache_disable()
194 if (value == 0) in __rt_ffs()
195 return value; in __rt_ffs()
210 if (value == 0) in __rt_ffs()
211 return value; in __rt_ffs()
221 if (value == 0) in __rt_ffs()
224 value &= (-value); in __rt_ffs()
[all …]
A Dmmu.c22 value = 0; in mmu_setttbase()
51 orr value, value, #0x01 in mmu_enable()
63 bic value, value, #0x01 in mmu_disable()
75 orr value, value, #0x1000 in mmu_enable_icache()
87 orr value, value, #0x04 in mmu_enable_dcache()
99 bic value, value, #0x1000 in mmu_disable_icache()
111 bic value, value, #0x04 in mmu_disable_dcache()
123 orr value, value, #0x02 in mmu_enable_alignfault()
135 bic value, value, #0x02 in mmu_disable_alignfault()
200 value = 0; in mmu_invalidate_tlb()
[all …]
A Dvfp.c20 unsigned int value; in vfp_init() local
22 :"=r"(value) in vfp_init()
24 value |= 0xf00000;/*enable CP10, CP11 user access*/ in vfp_init()
27 :"r"(value)); in vfp_init()
30 :"=r"(value)); in vfp_init()
31 value |=(1<<30); in vfp_init()
34 :"r"(value)); in vfp_init()
/libcpu/arm/s3c24x0/
A Dmmu.c189 register rt_uint32_t value; in mmu_enable() local
194 orr value, value, #0x01 in mmu_enable()
206 bic value, value, #0x01 in mmu_disable()
218 orr value, value, #0x1000 in mmu_enable_icache()
230 orr value, value, #0x04 in mmu_enable_dcache()
242 bic value, value, #0x1000 in mmu_disable_icache()
254 bic value, value, #0x04 in mmu_disable_dcache()
266 orr value, value, #0x02 in mmu_enable_alignfault()
278 bic value, value, #0x02 in mmu_disable_alignfault()
295 value = 0; in mmu_invalidate_tlb()
[all …]
A Dcpu.c70 rt_uint32_t value; in cache_enable() local
74 mrc p15, 0, value, c1, c0, 0 in cache_enable()
75 orr value, value, bit in cache_enable()
76 mcr p15, 0, value, c1, c0, 0 in cache_enable()
82 rt_uint32_t value; in cache_disable() local
86 mrc p15, 0, value, c1, c0, 0 in cache_disable()
87 bic value, value, bit in cache_disable()
88 mcr p15, 0, value, c1, c0, 0 in cache_disable()
/libcpu/risc-v/common64/
A Driscv.h22 #define __MASKVALUE(value,maskvalue) ((value) & (maskvalue)) argument
23 #define __UMASKVALUE(value,maskvalue) ((value) & (~(maskvalue))) argument
24 #define __CHECKUPBOUND(value,bit_count) (!(((rt_ubase_t)value) & (~__MASK(bit_count)))) argument
25 #define __CHECKALIGN(value,start_bit) (!(((rt_ubase_t)value) & (__MASK(start_bit)))) argument
27 #define __PARTBIT(value,start_bit,length) (((value) >> (start_bit)) & __MASK(length)) argument
29 #define __ALIGNUP(value,bit) (((value) + __MASK(bit)) & __UMASK(bit)) argument
30 #define __ALIGNDOWN(value,bit) ((value) & __UMASK(bit)) argument
/libcpu/arm/cortex-a/
A Dgtimer.c18 static inline void __set_cntfrq(rt_uint32_t value) in __set_cntfrq() argument
20 __set_cp(15, 0, value, 14, 0, 0); in __set_cntfrq()
40 __set_cp(15, 0, value, 14, 2, 0); in __set_cntp_tval()
71 __set_cp64(15, 2, value, 14); in __set_cntp_cval()
91 __set_cp(15, 0, value, 14, 2, 1); in __set_cntp_ctl()
109 __set_cntfrq(value); in gtimer_set_counter_frequency()
124 void gtimer_set_load_value(rt_uint32_t value) in gtimer_set_load_value() argument
126 __set_cntp_tval(value); in gtimer_set_load_value()
151 __set_cntp_cval(value); in gtimer_set_physical_compare_value()
166 void gtimer_set_control(rt_uint32_t value) in gtimer_set_control() argument
[all …]
A Dgtimer.h16 void gtimer_set_counter_frequency(rt_uint32_t value);
18 void gtimer_set_load_value(rt_uint32_t value);
21 void gtimer_set_physical_compare_value(rt_uint64_t value);
23 void gtimer_set_control(rt_uint32_t value);
A Dtrap.c282 uint32_t value = 0; in rt_hw_trap_irq() local
283 value = IRQ_PEND_BASIC & 0x3ff; in rt_hw_trap_irq()
307 if (value) in rt_hw_trap_irq()
309 if (value & (1 << 8)) in rt_hw_trap_irq()
311 value = IRQ_PEND1; in rt_hw_trap_irq()
312 irq = __rt_ffs(value) - 1; in rt_hw_trap_irq()
314 else if (value & (1 << 9)) in rt_hw_trap_irq()
316 value = IRQ_PEND2; in rt_hw_trap_irq()
317 irq = __rt_ffs(value) + 31; in rt_hw_trap_irq()
321 value &= 0x0f; in rt_hw_trap_irq()
[all …]
/libcpu/c-sky/common/
A Dcsi_instr.h117 __ALWAYS_INLINE uint32_t __REV(uint32_t value) in __REV() argument
119 return __builtin_bswap32(value); in __REV()
135 result = ((value & 0xFF000000) >> 8) | ((value & 0x00FF0000) << 8) | in __REV16()
136 ((value & 0x0000FF00) >> 8) | ((value & 0x000000FF) << 8); in __REV16()
148 __ALWAYS_INLINE int32_t __REVSH(int32_t value) in __REVSH() argument
150 return (short)(((value & 0xFF00) >> 8) | ((value & 0x00FF) << 8)); in __REVSH()
183 __ALWAYS_INLINE uint32_t __RBIT(uint32_t value) in __RBIT() argument
194 for (value >>= 1U; value; value >>= 1U) in __RBIT()
197 result |= value & 1U; in __RBIT()
275 result = value; in __USAT()
[all …]
/libcpu/arm/am335x/
A Dcpu.c40 rt_uint32_t value; in cache_enable() local
44 mrc p15, 0, value, c1, c0, 0 in cache_enable()
45 orr value, value, bit in cache_enable()
46 mcr p15, 0, value, c1, c0, 0 in cache_enable()
52 rt_uint32_t value; in cache_disable() local
56 mrc p15, 0, value, c1, c0, 0 in cache_disable()
57 bic value, value, bit in cache_disable()
58 mcr p15, 0, value, c1, c0, 0 in cache_disable()
A Dmmu.c55 register rt_uint32_t value; in mmu_setttbase() local
62 value = 0; in mmu_setttbase()
63 asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); in mmu_setttbase()
65 value = 0x55555555; in mmu_setttbase()
66 asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); in mmu_setttbase()
/libcpu/arm/cortex-r4/
A Dcpu.c21 int __rt_ffs(int value) in __rt_ffs() argument
23 if (value == 0) in __rt_ffs()
24 return value; in __rt_ffs()
72 int __rt_ffs(int value) in __rt_ffs() argument
74 return __builtin_ffs(value); in __rt_ffs()
/libcpu/arm/cortex-m3/
A Dcpuport.c380 int __rt_ffs(int value) in __rt_ffs() argument
392 : "=r"(value) in __rt_ffs()
393 : "r"(value) in __rt_ffs()
395 return value; in __rt_ffs()
398 int __rt_ffs(int value) in __rt_ffs() argument
400 if (value == 0) return value; in __rt_ffs()
402 asm("RBIT %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
403 asm("CLZ %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
404 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); in __rt_ffs()
406 return value; in __rt_ffs()
[all …]
/libcpu/arm/cortex-m4/
A Dcpuport.c464 int __rt_ffs(int value) in __rt_ffs() argument
476 : "=r"(value) in __rt_ffs()
477 : "r"(value) in __rt_ffs()
479 return value; in __rt_ffs()
482 int __rt_ffs(int value) in __rt_ffs() argument
484 if (value == 0) return value; in __rt_ffs()
486 asm("RBIT %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
487 asm("CLZ %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
488 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); in __rt_ffs()
490 return value; in __rt_ffs()
[all …]
/libcpu/arm/cortex-m33/
A Dcpuport.c546 int __rt_ffs(int value) in __rt_ffs() argument
548 if (value == 0) return value; in __rt_ffs()
555 : "=r"(value) in __rt_ffs()
556 : "r"(value) in __rt_ffs()
558 return value; in __rt_ffs()
561 int __rt_ffs(int value) in __rt_ffs() argument
563 if (value == 0) return value; in __rt_ffs()
565 asm("RBIT %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
566 asm("CLZ %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
567 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); in __rt_ffs()
[all …]
/libcpu/arm/cortex-m85/
A Dcpuport.c478 int __rt_ffs(int value) in __rt_ffs() argument
490 : "=r"(value) in __rt_ffs()
491 : "r"(value) in __rt_ffs()
493 return value; in __rt_ffs()
496 int __rt_ffs(int value) in __rt_ffs() argument
498 if (value == 0) return value; in __rt_ffs()
500 asm("RBIT %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
501 asm("CLZ %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
502 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); in __rt_ffs()
504 return value; in __rt_ffs()
[all …]
/libcpu/arm/cortex-m7/
A Dcpuport.c488 int __rt_ffs(int value) in __rt_ffs() argument
500 : "=r"(value) in __rt_ffs()
501 : "r"(value) in __rt_ffs()
503 return value; in __rt_ffs()
506 int __rt_ffs(int value) in __rt_ffs() argument
508 if (value == 0) return value; in __rt_ffs()
510 asm("RBIT %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
511 asm("CLZ %0, %1" : "=r"(value) : "r"(value)); in __rt_ffs()
512 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value)); in __rt_ffs()
514 return value; in __rt_ffs()
[all …]
/libcpu/arm/common/
A Datomic_arm.c58 #define __STREXW(value, ptr) __strex(value, ptr) argument
60 #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) … argument
63 _Pragma("inline=forced") __intrinsic rt_atomic_t __STREXW(rt_atomic_t value, volatile rt_atomic_t *… in __STREXW() argument
65 return __STREX(value, (unsigned int *)ptr); in __STREXW()
68 __attribute__((always_inline)) static inline rt_atomic_t __STREXW(volatile rt_atomic_t value, v… in __STREXW() argument
72 __asm volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); in __STREXW()

Completed in 35 milliseconds

123