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Searched refs:writel (Results 1 – 6 of 6) sorted by relevance

/libcpu/risc-v/t-head/c906/
A Dplic.c51 writel(enable, priority_addr); in plic_irq_toggle()
91 writel(irqno, (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM)); in plic_complete()
148 writel(readl(reg) | hwirq_mask, reg); in plic_toggle()
152 writel(readl(reg) & ~hwirq_mask, reg); in plic_toggle()
211 writel(threshold, (void *)((rt_size_t)handler->hart_base + CONTEXT_THRESHOLD)); in plic_init()
/libcpu/risc-v/t-head/c908/
A Dplic.c51 writel(enable, priority_addr); in plic_irq_toggle()
91 writel(irqno, (void *)((rt_size_t)handler->hart_base + CONTEXT_CLAIM)); in plic_complete()
148 writel(readl(reg) | hwirq_mask, reg); in plic_toggle()
152 writel(readl(reg) & ~hwirq_mask, reg); in plic_toggle()
211 writel(threshold, (void *)((rt_size_t)handler->hart_base + CONTEXT_THRESHOLD)); in plic_init()
/libcpu/risc-v/common64/
A Dio.h25 static inline void writel(uint32_t val, volatile void *addr) in writel() function
43 writel(val, (void *)((rt_size_t)addr + offset)); in write_reg()
A Driscv_io.h108 #define writel(v,c) ({ __io_bw(); __raw_writel((v),(c)); __io_aw(); }) macro
/libcpu/risc-v/virt64/
A Dplic.c119 writel(val, plic_ie); in plic_set_ie()
/libcpu/mips/common/
A Dmips_regs.h1142 #define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) macro

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