| /libcpu/c-sky/common/ |
| A D | csi_simd.h | 99 r = __IUSAT(((x << 16) >> 16), y) & 0x0000FFFF; in __USAT16()
100 s = __IUSAT(((x) >> 16), y) & 0x0000FFFF; in __USAT16()
212 u = (((x) >> 24) + ((y) >> 24)) & 0x000000FF; in __UADD8()
324 u = (((x) >> 24) - ((y) >> 24)) & 0x000000FF; in __USUB8()
1134 if (x + y >= x) in __QADD()
1136 result = x + y; in __QADD()
1145 if (x + y < x) in __QADD()
1147 result = x + y; in __QADD()
1172 tmp = (int64_t)x - (int64_t)y; in __QSUB()
1460 __ALWAYS_INLINE uint32_t __SXTB16(uint32_t x) in __SXTB16() argument
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| A D | csi_instr.h | 220 __ALWAYS_INLINE int32_t __SSAT(int32_t x, uint32_t y) in __SSAT() argument
232 if (x > 0) in __SSAT()
236 if (x > posMax) in __SSAT()
238 x = posMax; in __SSAT()
247 if (x < negMin) in __SSAT()
249 x = negMin; in __SSAT()
255 return (x); in __SSAT()
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| /libcpu/ti-dsp/c6x/ |
| A D | trap.h | 81 #define ffz(x) __ffs(~(x)) argument
90 static inline int fls(int x) in fls() argument
92 if (!x) in fls()
96 return 32 - __fls(x); in fls()
108 static inline int ffs(int x) in ffs() argument
110 if (!x) in ffs()
114 return __ffs(x) + 1; in ffs()
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| /libcpu/mips/common/ |
| A D | mips_addrspace.h | 22 #define _CONST64_(x) x argument
28 #define _CONST64_(x) x ## L argument
30 #define _CONST64_(x) x ## LL argument
151 #define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ argument
153 #define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) argument
154 #define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) argument
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| A D | mips_regs.h | 144 #define __STR(x) #x argument
147 #define STR(x) __STR(x) argument
654 #define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE) argument
655 #define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2)) argument
1129 #define set_cp0_status(x) set_c0_status(x) argument
1130 #define set_cp0_cause(x) set_c0_cause(x) argument
1131 #define set_cp0_config(x) set_c0_config(x) argument
1134 #define write_c1_status(x) write_32bit_cp1_register(31, x) argument
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| /libcpu/arm/arm926/ |
| A D | cpuport.c | 191 register rt_uint32_t x; in __rt_ffs() local
198 rsb x, value, #0 in __rt_ffs()
199 and x, x, value in __rt_ffs()
200 clz x, x in __rt_ffs()
201 rsb x, x, #32 in __rt_ffs()
204 return x; in __rt_ffs()
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| /libcpu/arm/dm36x/ |
| A D | cpuport.c | 190 register rt_uint32_t x; in __rt_ffs() local
197 rsb x, value, #0 in __rt_ffs()
198 and x, x, value in __rt_ffs()
199 clz x, x in __rt_ffs()
200 rsb x, x, #32 in __rt_ffs()
203 return x; in __rt_ffs()
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| A D | mmu.h | 28 #define PGD_DOMAIN(x) ((x) << 5) argument
38 #define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ argument
76 #define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ argument
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| /libcpu/arm/armv6/ |
| A D | cpuport.c | 192 register rt_uint32_t x; in __rt_ffs() local
199 rsb x, value, #0 in __rt_ffs()
200 and x, x, value in __rt_ffs()
201 clz x, x in __rt_ffs()
202 rsb x, x, #32 in __rt_ffs()
205 return x; in __rt_ffs()
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| A D | mmu.h | 28 #define PGD_DOMAIN(x) ((x) << 5) argument
38 #define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ argument
76 #define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ argument
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| /libcpu/mips/gs264/ |
| A D | mmu.h | 61 #define MMU_MAP_MTBL_AP01(x) (x<<4) argument
62 #define MMU_MAP_MTBL_TEX(x) (x<<6) argument
63 #define MMU_MAP_MTBL_AP2(x) (x<<9) argument
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| A D | mips_mmu.h | 77 #define lowbit(x) ((x) & (-(x))) argument
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| /libcpu/arm/cortex-a/ |
| A D | mmu.h | 63 #define MMU_MAP_MTBL_AP01(x) (x<<4) argument
64 #define MMU_MAP_MTBL_TEX(x) (x<<6) argument
65 #define MMU_MAP_MTBL_AP2(x) (x<<9) argument
67 #define MMU_MAP_MTBL_NG(x) (x<<11) argument
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| A D | gicv3.h | 48 #define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x))) argument
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| /libcpu/ppc/ppc405/include/asm/ |
| A D | processor.h | 134 #define DBCR_RST(x) (((x) & 0x3) << 28) argument
149 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ argument
156 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ argument
383 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ argument
388 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ argument
395 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ argument
420 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ argument
790 #define IOCR_RDM(x) (((x) & 0x3) << 3) argument
1076 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} argument
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| /libcpu/blackfin/bf53x/ |
| A D | context_vdsp.S | 79 R1.L = A0.x;
83 R1.L = A1.x;
126 A1.x = R0.L;
130 A0.x = R0.L;
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| /libcpu/arm/am335x/ |
| A D | am33xx.h | 12 #define REG32(x) (*((volatile unsigned int *)(x))) argument
13 #define REG16(x) (*((volatile unsigned short *)(x))) argument
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| /libcpu/arm/cortex-r52/ |
| A D | gicv3.h | 48 #define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x))) argument
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| A D | cp15_gcc.S | 64 add r2, r10, r10, lsr #1 @ work out 3x current cache level
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| /libcpu/v850/70f34/ |
| A D | context_iar.S | 11 ; Right now, all TRAPs to $1x are trated the same way
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| A D | context_iar.asm | 11 ; Right now, all TRAPs to $1x are trated the same way
|