| /libcpu/aarch64/common/ |
| A D | cpu_gcc.S | 48 lsr x0, x0, #8
50 and x0, x0, #15
78 mov x0, xzr
142 and x0, x0, #0xc0
158 and x0, x0, #0xc0
166 and x0, x0, #0xc0
169 orr x0, x0, x1
232 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
237 orr x0, x0, #0x38
259 sub x0, x1, x0
[all …]
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| A D | cache.S | 66 mov x1, x0
88 add x0, x0, #1 /* increment cache level */
92 mov x0, #0
103 mov x0, #0
129 bic x0, x0, x3
132 add x0, x0, x2
133 cmp x0, x1
155 bic x0, x0, x3
158 add x0, x0, x2
180 bic x0, x0, x3
[all …]
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| A D | vector_gcc.S | 76 SAVE_USER_CTX EFRAMEX, x0
78 mov x0, EFRAMEX
80 RESTORE_USER_CTX EFRAMEX, x0
83 EXCEPTION_SWITCH sp, x0
93 SAVE_USER_CTX EFRAMEX, x0
95 mov x0, EFRAMEX
98 RESTORE_USER_CTX EFRAMEX, x0
110 SAVE_USER_CTX EFRAMEX, x0
113 mov x0, EFRAMEX
121 mov x0, EFRAMEX
[all …]
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| A D | stack_gcc.S | 24 mov x0, x21
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| A D | smccc.S | 19 stp x0, x1, [x4, #0]
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| A D | trap.c | 156 …rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)… in rt_hw_show_register()
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| /libcpu/aarch64/cortex-a/ |
| A D | entry_point.S | 149 cmp x3, x0
163 sub x0, x0, #1
178 lsr x0, x0, #2
179 and x0, x0, #3
182 cmp x0, #3
217 orr x0, x0, #(1 << 1) /* SWIO hardwired */
221 orr x0, x0, #(1 << 6) /* Mask FIQ */
222 orr x0, x0, #(1 << 7) /* Mask IRQ */
223 orr x0, x0, #(1 << 8) /* Mask SError */
224 orr x0, x0, #(1 << 9) /* Mask Debug Exception */
[all …]
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| /libcpu/aarch64/common/mp/ |
| A D | context_gcc.S | 42 ldr x0, [x0]
43 mov sp, x0
49 mov x0, x19
52 mov x0, x19
71 mov sp, x0
77 mov x0, x19
80 mov x0, x19
112 GET_THREAD_SELF x0
124 mov x0, sp
129 mov sp, x0
[all …]
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| A D | context_gcc.h | 52 ldp x0, x1, [sp], #0x10
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| /libcpu/aarch64/common/up/ |
| A D | context_gcc.S | 46 ldr x0, [x0]
47 RESTORE_CONTEXT_SWITCH x0
62 str x2, [x0] // store sp in preempted tasks TCB
63 ldr x0, [x1] // get new task stack pointer
65 RESTORE_CONTEXT_SWITCH x0
84 str x0, [x4]
92 mov x0, x2
112 mov x0, sp
113 str x0, [x4] // store sp in preempted tasks's tcb
117 ldr x0, [x4] // get new task's stack pointer
[all …]
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| A D | context_gcc.h | 26 mov x19, x0
28 mov x0, x19
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| /libcpu/aarch64/common/include/ |
| A D | asm-generic.h | 36 mrs x0, tpidr_el1
40 .if \dst != x0
41 mov dst, x0
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| A D | vector_gcc.h | 24 stp x0, x1, [sp, #-0x10]!
82 ldp x0, x1, [sp], #0x10
110 mov x0, \eframex
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| A D | armv8.h | 142 rt_uint64_t x0; member
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| /libcpu/risc-v/vector/rvv-1.0/ |
| A D | rvv_context.h | 66 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
88 VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8)
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| A D | vector_encoding.h | 51 #define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype
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| /libcpu/risc-v/t-head/c906/ |
| A D | opcode.h | 41 __OPC_INSN_FORMAT_R(0x0b, 0x0, func7, x0, rs1, rs2)
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| /libcpu/risc-v/t-head/c908/ |
| A D | opcode.h | 42 __OPC_INSN_FORMAT_R(0x0b, 0x0, func7, x0, rs1, rs2)
|