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Searched refs:x1 (Results 1 – 17 of 17) sorted by relevance

/libcpu/aarch64/cortex-a/
A Dentry_point.S138 add x1, x1, x2
187 orr x1, x1, #(1 << 4) /* RES1 */
188 orr x1, x1, #(1 << 5) /* RES1 */
193 orr x1, x1, #(1 << 6) /* Mask FIQ */
194 orr x1, x1, #(1 << 7) /* Mask IRQ */
195 orr x1, x1, #(1 << 8) /* Mask SError */
196 orr x1, x1, #(1 << 9) /* Mask Debug Exception */
308 get_pvoff x1 x0
310 sub x1, x1, x0
311 mov sp, x1
[all …]
/libcpu/aarch64/common/
A Dcpu_gcc.S167 mrs x1, DAIF
168 bic x1, x1, #0xc0
201 cmp x1, 0xc
203 cmp x1, 0x8
205 cmp x1, 0x4
223 cmp x1, 0xc
225 cmp x1, 0x8
227 cmp x1, 0x4
256 mvn x1, x0
257 clz x0, x1
[all …]
A Dcache.S66 mov x1, x0
133 cmp x0, x1
159 cmp x0, x1
184 cmp x0, x1
A Dsmccc.S19 stp x0, x1, [x4, #0]
A Dtrap.c156 …:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (… in rt_hw_show_register()
/libcpu/aarch64/common/up/
A Dvector_gcc.S49 ldr x1, =rt_thread_switch_interrupt_flag
50 ldr x2, [x1]
56 str x2, [x1]
A Dcontext_gcc.S63 ldr x0, [x1] // get new task stack pointer
90 stp x1, x30, [sp, #-0x10]!
95 ldp x1, x30, [sp], #0x10
98 str x1, [x6]
/libcpu/aarch64/common/mp/
A Dcontext_gcc.S44 update_tidr x1
47 mov x19, x1
70 ldr x0, [x1] // get new task stack pointer
107 mov FROM_SPP, x1
A Dcontext_gcc.h52 ldp x0, x1, [sp], #0x10
/libcpu/risc-v/common64/
A Dstartup_gcc.S45 li x1, 0
105 la x1, _after_pc_relocation
106 sub x1, x1, a0
A Dstackframe.h80 STORE x1, 1 * REGBYTES(sp)
82 csrr x1, sstatus
83 STORE x1, FRAME_OFF_SSTATUS(sp)
85 csrr x1, sepc
86 STORE x1, 0 * REGBYTES(sp)
255 LOAD x1, 0 * REGBYTES(sp)
256 csrw sepc, x1
258 LOAD x1, 2 * REGBYTES(sp)
259 csrw sstatus, x1
261 LOAD x1, 1 * REGBYTES(sp)
/libcpu/aarch64/common/include/
A Dhypercall.h21 rt_inline rt_uint32_t rt_hw_hypercall(rt_uint32_t w0, rt_uint64_t x1, rt_uint64_t x2, in rt_hw_hypercall() argument
26 arm_smccc_hvc(w0, x1, x2, x3, x4, x5, x6, w7, &res, RT_NULL); in rt_hw_hypercall()
A Dvector_gcc.h24 stp x0, x1, [sp, #-0x10]!
82 ldp x0, x1, [sp], #0x10
A Darmv8.h143 rt_uint64_t x1; member
/libcpu/risc-v/rv64/
A Dtrap.c18 uint64_t x1; member
56 …x1 (ra : Return address ) ==> 0x%08x%08x\n", esf->x1 >> 32 , esf->x1 & UINT32_MA… in print_stack_frame()
/libcpu/risc-v/common/
A Dinterrupt_gcc.S67 STORE x1, 1 * REGBYTES(sp)
133 LOAD x1, 1 * REGBYTES(sp)
264 STORE x1, 1 * REGBYTES(sp)
266 csrr x1, mstatus
267 STORE x1, 2 * REGBYTES(sp)
269 csrr x1, mepc
270 STORE x1, 0 * REGBYTES(sp)
A Dcontext_gcc.S139 STORE x1, 0 * REGBYTES(sp)
140 STORE x1, 1 * REGBYTES(sp)
237 LOAD x1, 1 * REGBYTES(sp)

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