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Searched refs:x12 (Results 1 – 10 of 10) sorted by relevance

/libcpu/aarch64/common/
A Dcache.S22 lsl x12, x0, #1
23 msr csselr_el1, x12 /* select cache level */
43 orr x9, x12, x7 /* map way and level to cisw value */
80 lsl x12, x0, #1
81 add x12, x12, x0 /* x0 <- tripled cache level */
82 lsr x12, x10, x12
83 and x12, x12, #7 /* x12 <- cache type */
84 cmp x12, #2
A Dtrap.c159 …rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *… in rt_hw_show_register()
/libcpu/risc-v/rv64/
A Dtrap.c29 uint64_t x12; member
67 …12(a2 : Function argument ) ==> 0x%08x%08x\n", esf->x12 >> 32 , esf->x12 & UINT32_MA… in print_stack_frame()
/libcpu/aarch64/common/include/
A Dvector_gcc.h30 stp x12, x13, [sp, #-0x10]!
76 ldp x12, x13, [sp], #0x10
A Darmv8.h130 rt_uint64_t x12; member
/libcpu/aarch64/common/mp/
A Dcontext_gcc.h46 ldp x12, x13, [sp], #0x10
/libcpu/risc-v/common64/
A Dstartup_gcc.S56 li x12,0
A Dstackframe.h97 STORE x12, 12 * REGBYTES(sp)
272 LOAD x12, 12 * REGBYTES(sp)
/libcpu/risc-v/common/
A Dinterrupt_gcc.S78 STORE x12, 12 * REGBYTES(sp)
149 LOAD x12, 12 * REGBYTES(sp)
280 STORE x12, 12 * REGBYTES(sp)
A Dcontext_gcc.S157 STORE x12, 12 * REGBYTES(sp)
255 LOAD x12, 12 * REGBYTES(sp)

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