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Searched refs:x6 (Results 1 – 14 of 14) sorted by relevance

/libcpu/aarch64/common/up/
A Dcontext_gcc.S77 ldr x6, =rt_thread_switch_interrupt_flag
78 ldr x7, [x6]
88 str x7, [x6]
97 ldr x6, =rt_interrupt_to_thread // set rt_interrupt_to_thread
98 str x1, [x6]
/libcpu/aarch64/common/
A Dcache.S25 mrs x6, ccsidr_el1 /* read the new cssidr_el1 */
26 and x2, x6, #7 /* x2 <- log2(cache line size)-4 */
29 and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
32 and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
40 mov x6, x3 /* x6 <- working copy of #ways */
42 lsl x7, x6, x5
50 2: subs x6, x6, #1 /* decrement the way */
A Dtrap.c157 …x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7); in rt_hw_show_register()
/libcpu/aarch64/common/include/
A Dhypercall.h22 rt_uint64_t x3, rt_uint64_t x4, rt_uint64_t x5, rt_uint64_t x6, rt_uint32_t w7) in rt_hw_hypercall() argument
26 arm_smccc_hvc(w0, x1, x2, x3, x4, x5, x6, w7, &res, RT_NULL); in rt_hw_hypercall()
A Dvector_gcc.h27 stp x6, x7, [sp, #-0x10]!
79 ldp x6, x7, [sp], #0x10
A Darmv8.h136 rt_uint64_t x6; member
/libcpu/risc-v/rv64/
A Dtrap.c23 uint64_t x6; member
61 …x6 (t1 : Temporary ) ==> 0x%08x%08x\n", esf->x6 >> 32 , esf->x6 & UINT32_MA… in print_stack_frame()
/libcpu/risc-v/t-head/c906/
A Dopcode.h69 #define OPC_DCACHE_IVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x6, rs1)
/libcpu/risc-v/t-head/c908/
A Dopcode.h77 #define OPC_DCACHE_IVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x6, rs1)
/libcpu/aarch64/common/mp/
A Dcontext_gcc.h49 ldp x6, x7, [sp], #0x10
/libcpu/risc-v/common64/
A Dstartup_gcc.S50 li x6, 0
A Dstackframe.h91 STORE x6, 6 * REGBYTES(sp)
266 LOAD x6, 6 * REGBYTES(sp)
/libcpu/risc-v/common/
A Dinterrupt_gcc.S72 STORE x6, 6 * REGBYTES(sp)
143 LOAD x6, 6 * REGBYTES(sp)
274 STORE x6, 6 * REGBYTES(sp)
A Dcontext_gcc.S151 STORE x6, 6 * REGBYTES(sp)
249 LOAD x6, 6 * REGBYTES(sp)

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