Searched refs:x7 (Results 1 – 14 of 14) sorted by relevance
| /libcpu/aarch64/common/up/ |
| A D | context_gcc.S | 78 ldr x7, [x6]
79 cmp x7, #1
87 mov x7, #1
88 str x7, [x6]
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| /libcpu/aarch64/common/ |
| A D | cache.S | 42 lsl x7, x6, x5
43 orr x9, x12, x7 /* map way and level to cisw value */
44 lsl x7, x4, x2
45 orr x9, x9, x7 /* map set number to cisw value */
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| A D | trap.c | 157 …x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7); in rt_hw_show_register()
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| /libcpu/risc-v/rv64/ |
| A D | trap.c | 24 uint64_t x7; member
62 …x7 (t2 : Temporary ) ==> 0x%08x%08x\n", esf->x7 >> 32 , esf->x7 & UINT32_MA… in print_stack_frame()
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| /libcpu/aarch64/common/include/ |
| A D | vector_gcc.h | 27 stp x6, x7, [sp, #-0x10]!
79 ldp x6, x7, [sp], #0x10
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| A D | armv8.h | 137 rt_uint64_t x7; member
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| /libcpu/risc-v/t-head/c906/ |
| A D | opcode.h | 70 #define OPC_DCACHE_CIVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x7, rs1)
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| /libcpu/risc-v/t-head/c908/ |
| A D | opcode.h | 78 #define OPC_DCACHE_CIVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x7, rs1)
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| /libcpu/aarch64/common/mp/ |
| A D | context_gcc.h | 49 ldp x6, x7, [sp], #0x10
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| /libcpu/risc-v/common64/ |
| A D | startup_gcc.S | 51 li x7, 0
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| A D | stackframe.h | 92 STORE x7, 7 * REGBYTES(sp)
267 LOAD x7, 7 * REGBYTES(sp)
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| /libcpu/risc-v/common/ |
| A D | readme.md | 142 rt_hw_interrupt_install(0x7, timer_irq_handler, RT_NULL, "timerirq");//注册系统定时器中断入口函数
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| A D | interrupt_gcc.S | 73 STORE x7, 7 * REGBYTES(sp)
144 LOAD x7, 7 * REGBYTES(sp)
275 STORE x7, 7 * REGBYTES(sp)
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| A D | context_gcc.S | 152 STORE x7, 7 * REGBYTES(sp)
250 LOAD x7, 7 * REGBYTES(sp)
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