1 /* 2 * Allwinner SoCs display driver. 3 * 4 * Copyright (C) 2016 Allwinner. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #ifndef _DISP_INCLUDE_H_ 12 #define _DISP_INCLUDE_H_ 13 14 #include <typedef.h> 15 #include <stdbool.h> 16 #include <hal_sem.h> 17 #include <hal_clk.h> 18 #include <log.h> 19 #include <aw_list.h> 20 #include <hal_sem.h> 21 #include <hal_gpio.h> 22 #include <sunxi_hal_pwm.h> 23 #include <hal_atomic.h> 24 #include <workqueue.h> 25 #include <video/sunxi_display2.h> 26 #include <video/sunxi_metadata.h> 27 #include "../disp_sys_intf.h" 28 #include <hal_mem.h> 29 #include <hal_queue.h> 30 #include <hal_log.h> 31 #include "disp_features.h" 32 33 34 35 36 #define DISP2_DEBUG_LEVEL 1 37 38 #if DISP2_DEBUG_LEVEL == 1 39 #define DE_INF(fmt, ...) do {hal_log_info("disp:[%s %d]"fmt, __func__, __LINE__, ##__VA_ARGS__);} while (0) 40 #define DE_MSG(fmt, ...) do {hal_log_info("disp:[%s %d]"fmt, __func__, __LINE__, ##__VA_ARGS__);} while (0) 41 #define DE_HERE 42 #define DE_DBG(fmt, ...) do {hal_log_debug("disp:[%s %d]"fmt, __func__, __LINE__, ##__VA_ARGS__);} while (0) 43 #elif DISP2_DEBUG_LEVEL == 2 44 #define DE_INF(...) hal_log_info(__VA_ARGS__) 45 #define DE_HERE(...) hal_log_info(__VA_ARGS__) 46 #define DE_DBG(...) hal_log_debug(__VA_ARGS__) 47 #else 48 #define DE_INF(msg...) asm("nop") 49 #define DE_MSG(msg...) asm("nop") 50 #define DE_HERE asm("nop") 51 #define DE_DBG(msg...) asm("nop") 52 #endif 53 54 #define DE_WRN(fmt, ...) do {hal_log_warn("disp:[%s %d]"fmt, __func__, __LINE__, ##__VA_ARGS__);} while (0) 55 56 #define DISP_PRINT printf 57 58 #define DISP_IRQ_RETURN DIS_SUCCESS 59 60 61 #define DEFAULT_PRINT_LEVLE 0 62 #if defined(CONFIG_FPGA_V4_PLATFORM) \ 63 || defined(CONFIG_FPGA_V7_PLATFORM) \ 64 || defined(CONFIG_A67_FPGA) 65 #define __FPGA_DEBUG__ 66 #endif 67 68 #define SETMASK(width, shift) ((width?((-1U) >> (32-width)):0) << (shift)) 69 #define CLRMASK(width, shift) (~(SETMASK(width, shift))) 70 #define GET_BITS(shift, width, reg) \ 71 (((reg) & SETMASK(width, shift)) >> (shift)) 72 #define SET_BITS(shift, width, reg, val) \ 73 (((reg) & CLRMASK(width, shift)) | (val << (shift))) 74 75 #define DISPALIGN(value, align) ((align == 0) ? \ 76 value : \ 77 (((value) + ((align) - 1)) & ~((align) - 1))) 78 79 #ifndef abs 80 #define abs(x) (((x)&0x80000000) ? (0-(x)):(x)) 81 #endif 82 83 #define LCD_GAMMA_TABLE_SIZE (256 * sizeof(unsigned int)) 84 85 #define ONE_SEC 1000000000ull 86 87 #undef readl 88 #define readl(addr) (*((volatile unsigned int *)(addr))) 89 #undef writel 90 #define writel(v, addr) (*((volatile unsigned int *)(addr)) = (unsigned int)(v)) 91 92 93 typedef hal_clk_id_t disp_clk_t; 94 95 struct panel_extend_para { 96 u32 lcd_gamma_en; 97 u32 lcd_gamma_tbl[256]; 98 u32 lcd_cmap_en; 99 u32 lcd_cmap_tbl[2][3][4]; 100 u32 lcd_bright_curve_tbl[256]; 101 }; 102 103 enum disp_return_value { 104 DIS_SUCCESS = 0, 105 DIS_FAIL = -1, 106 DIS_PARA_FAILED = -2, 107 DIS_PRIO_ERROR = -3, 108 DIS_OBJ_NOT_INITED = -4, 109 DIS_NOT_SUPPORT = -5, 110 DIS_NO_RES = -6, 111 DIS_OBJ_COLLISION = -7, 112 DIS_DEV_NOT_INITED = -8, 113 DIS_DEV_SRAM_COLLISION = -9, 114 DIS_TASK_ERROR = -10, 115 DIS_PRIO_COLLSION = -11 116 }; 117 118 /*basic data information definition*/ 119 enum disp_layer_feat { 120 DISP_LAYER_FEAT_GLOBAL_ALPHA = 1 << 0, 121 DISP_LAYER_FEAT_PIXEL_ALPHA = 1 << 1, 122 DISP_LAYER_FEAT_GLOBAL_PIXEL_ALPHA = 1 << 2, 123 DISP_LAYER_FEAT_PRE_MULT_ALPHA = 1 << 3, 124 DISP_LAYER_FEAT_COLOR_KEY = 1 << 4, 125 DISP_LAYER_FEAT_ZORDER = 1 << 5, 126 DISP_LAYER_FEAT_POS = 1 << 6, 127 DISP_LAYER_FEAT_3D = 1 << 7, 128 DISP_LAYER_FEAT_SCALE = 1 << 8, 129 DISP_LAYER_FEAT_DE_INTERLACE = 1 << 9, 130 DISP_LAYER_FEAT_COLOR_ENHANCE = 1 << 10, 131 DISP_LAYER_FEAT_DETAIL_ENHANCE = 1 << 11, 132 }; 133 134 enum disp_pixel_type { 135 DISP_PIXEL_TYPE_RGB = 0x0, 136 DISP_PIXEL_TYPE_YUV = 0x1, 137 }; 138 139 enum disp_layer_dirty_flags { 140 LAYER_ATTR_DIRTY = 0x00000001, 141 LAYER_VI_FC_DIRTY = 0x00000002, 142 LAYER_HADDR_DIRTY = 0x00000004, 143 LAYER_SIZE_DIRTY = 0x00000008, 144 BLEND_ENABLE_DIRTY = 0x00000010, 145 BLEND_ATTR_DIRTY = 0x00000020, 146 BLEND_CTL_DIRTY = 0x00000040, 147 BLEND_OUT_DIRTY = 0x00000080, 148 LAYER_ATW_DIRTY = 0x00000100, 149 LAYER_HDR_DIRTY = 0x00000200, 150 LAYER_ALL_DIRTY = 0x000003ff, 151 }; 152 153 enum disp_manager_dirty_flags { 154 MANAGER_ENABLE_DIRTY = 0x00000001, 155 MANAGER_CK_DIRTY = 0x00000002, 156 MANAGER_BACK_COLOR_DIRTY = 0x00000004, 157 MANAGER_SIZE_DIRTY = 0x00000008, 158 MANAGER_COLOR_RANGE_DIRTY = 0x00000010, 159 MANAGER_COLOR_SPACE_DIRTY = 0x00000020, 160 MANAGER_BLANK_DIRTY = 0x00000040, 161 MANAGER_KSC_DIRTY = 0x00000080, 162 MANAGER_PALETTE_DIRTY = 0x00000100, 163 MANAGER_ALL_DIRTY = 0x00000fff, 164 }; 165 166 /* disp_atw_info_inner - asynchronous time wrap infomation 167 * 168 * @used: indicate if the atw funtion is used 169 * @mode: atw mode 170 * @b_row: the row number of the micro block 171 * @b_col: the column number of the micro block 172 * @cof_fd: dma_buf fd for the buffer contaied coefficient for atw 173 */ 174 struct disp_atw_info_inner { 175 bool used; 176 enum disp_atw_mode mode; 177 unsigned int b_row; 178 unsigned int b_col; 179 int cof_fd; 180 unsigned long long cof_addr; 181 }; 182 183 /* disp_fb_info_inner - image buffer info on the inside 184 * 185 * @addr: buffer address for each plane 186 * @size: size<width,height> for each buffer, unit:pixels 187 * @align: align for each buffer, unit:bytes 188 * @format: pixel format 189 * @color_space: color space 190 * @trd_right_addr: the right-eye buffer address for each plane, 191 * valid when frame-packing 3d buffer input 192 * @pre_multiply: indicate the pixel use premultiplied alpha 193 * @crop: crop rectangle for buffer to be display 194 * @flag: indicate stereo/non-stereo buffer 195 * @scan: indicate interleave/progressive scan type, and the scan order 196 * @metadata_buf: the phy_address to the buffer contained metadata for fbc/hdr 197 * @metadata_size: the size of metadata buffer, unit:bytes 198 * @metadata_flag: the flag to indicate the type of metadata buffer 199 * 0 : no metadata 200 * 1 << 0: hdr static metadata 201 * 1 << 1: hdr dynamic metadata 202 * 1 << 4: frame buffer compress(fbc) metadata 203 * x : all type could be "or" together 204 */ 205 struct disp_fb_info_inner { 206 int fd; 207 struct dma_buf *dmabuf; 208 unsigned long long addr[3]; 209 struct disp_rectsz size[3]; 210 unsigned int align[3]; 211 enum disp_pixel_format format; 212 enum disp_color_space color_space; 213 int trd_right_fd; 214 unsigned int trd_right_addr[3]; 215 bool pre_multiply; 216 struct disp_rect64 crop; 217 enum disp_buffer_flags flags; 218 enum disp_scan_flags scan; 219 enum disp_eotf eotf; 220 int depth; 221 unsigned int fbd_en; 222 unsigned int lbc_en; 223 int metadata_fd; 224 unsigned long long metadata_buf; 225 unsigned int metadata_size; 226 unsigned int metadata_flag; 227 struct disp_lbc_info lbc_info; 228 }; 229 230 /* disp_layer_info_inner - layer info on the inside 231 * 232 * @mode: buffer/clolor mode, when in color mode, the layer is widthout buffer 233 * @zorder: the zorder of layer, 0~max-layer-number 234 * @alpha_mode: 235 * 0: pixel alpha; 236 * 1: global alpha 237 * 2: mixed alpha, compositing width pixel alpha before global alpha 238 * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha 239 * @screen_win: the rectangle on the screen for fb to be display 240 * @b_trd_out: indicate if 3d display output 241 * @out_trd_mode: 3d output mode, valid when b_trd_out is true 242 * @color: the color value to be display, valid when layer is in color mode 243 * @fb: the framebuffer info related width the layer, valid when in buffer mode 244 * @id: frame id, the user could get the frame-id display currently by 245 * DISP_LAYER_GET_FRAME_ID ioctl 246 * @atw: asynchronous time wrap information 247 */ 248 struct disp_layer_info_inner { 249 enum disp_layer_mode mode; 250 unsigned char zorder; 251 unsigned char alpha_mode; 252 unsigned char alpha_value; 253 struct disp_rect screen_win; 254 bool b_trd_out; 255 enum disp_3d_out_mode out_trd_mode; 256 union { 257 unsigned int color; 258 struct disp_fb_info_inner fb; 259 }; 260 261 unsigned int id; 262 struct disp_atw_info_inner atw; 263 }; 264 265 /* disp_layer_config_inner - layer config on the inside 266 * 267 * @info: layer info 268 * @enable: indicate to enable/disable the layer 269 * @channel: the channel index of the layer, 0~max-channel-number 270 * @layer_id: the layer index of the layer widthin it's channel 271 */ 272 struct disp_layer_config_inner { 273 struct disp_layer_info_inner info; 274 bool enable; 275 unsigned int channel; 276 unsigned int layer_id; 277 }; 278 279 /* disp_layer_config_ops - operations for layer config 280 * 281 * @vmap:vmap a block contigous phys memory into virtual space 282 * @vunmap: release virtual mapping obtained by vmap() 283 */ 284 struct disp_layer_config_ops { 285 void *(*vmap)(unsigned long phys_addr, unsigned long size); 286 void (*vunmap)(const void *vaddr); 287 }; 288 struct disp_layer_config_data { 289 struct disp_layer_config_inner config; 290 enum disp_layer_dirty_flags flag; 291 struct disp_layer_config_ops ops; 292 }; 293 294 struct disp_manager_info { 295 struct disp_color back_color; 296 struct disp_colorkey ck; 297 struct disp_rect size; 298 enum disp_csc_type cs; 299 enum disp_color_space color_space; 300 u32 color_range; 301 u32 interlace; 302 bool enable; 303 /* index of device */ 304 u32 disp_device; 305 /* indicate the index of timing controller */ 306 u32 hwdev_index; 307 /* true: disable all layer; false: enable layer if requested */ 308 bool blank; 309 u32 de_freq; 310 enum disp_eotf eotf; /* sdr/hdr10/hlg */ 311 enum disp_data_bits data_bits; 312 struct disp_palette_config palette; 313 }; 314 315 struct disp_manager_data { 316 struct disp_manager_info config; 317 enum disp_manager_dirty_flags flag; 318 }; 319 320 struct disp_clk_info { 321 u32 clk; 322 u32 clk_div; 323 u32 h_clk; 324 u32 clk_src; 325 u32 clk_div2; 326 327 u32 clk_p; 328 u32 clk_div_p; 329 u32 h_clk_p; 330 u32 clk_src_p; 331 332 u32 ahb_clk; 333 u32 h_ahb_clk; 334 u32 dram_clk; 335 u32 h_dram_clk; 336 337 bool enabled; 338 }; 339 340 struct disp_enhance_info { 341 /* basic adjust */ 342 /* 343 * enhance parameters : 0~10, bigger value, stronger enhance level 344 * mode : combination of enhance_mode and dev_type 345 * enhance_mode : bit31~bit16 of mode 346 * : 0-disable; 1-enable; 2-demo(enable half window) 347 * dev_type : bit15~bit0 of mode 348 * : 0-lcd; 1-tv(hdmi, cvbs, vga, ypbpr) 349 */ 350 u32 bright; 351 u32 contrast; 352 u32 saturation; 353 u32 hue; 354 u32 edge; 355 u32 detail; 356 u32 denoise; 357 u32 mode; 358 /* ehnance */ 359 u32 sharp; /* 0-off; 1~3-on. */ 360 u32 auto_contrast; /* 0-off; 1~3-on. */ 361 u32 auto_color; /* 0-off; 1-on. */ 362 u32 fancycolor_red; /* 0-Off; 1-2-on. */ 363 u32 fancycolor_green; /* 0-Off; 1-2-on. */ 364 u32 fancycolor_blue; /* 0-Off; 1-2-on. */ 365 struct disp_rect window; 366 u32 enable; 367 struct disp_rect size; 368 u32 demo_enable; /* 1: enable demo mode */ 369 }; 370 371 enum disp_enhance_dirty_flags { 372 ENH_NONE_DIRTY = 0x0, 373 ENH_ENABLE_DIRTY = 0x1 << 0, /* enable dirty */ 374 ENH_SIZE_DIRTY = 0x1 << 1, /* size dirty */ 375 ENH_FORMAT_DIRTY = 0x1 << 2, /* overlay format dirty */ 376 ENH_BYPASS_DIRTY = 0x1 << 3, /* bypass dirty */ 377 ENH_INIT_DIRTY = 0x1 << 8, /* initial parameters dirty */ 378 ENH_MODE_DIRTY = 0X1 << 9, /* enhance mode dirty */ 379 ENH_BRIGHT_DIRTY = 0x1 << 10, /* brightness level dirty */ 380 ENH_CONTRAST_DIRTY = 0x1 << 11, /* contrast level dirty */ 381 ENH_EDGE_DIRTY = 0x1 << 12, /* edge level dirty */ 382 ENH_DETAIL_DIRTY = 0x1 << 13, /* detail level dirty */ 383 ENH_SAT_DIRTY = 0x1 << 14, /* saturation level dirty */ 384 ENH_DNS_DIRTY = 0x1 << 15, /* de-noise level dirty */ 385 ENH_USER_DIRTY = 0xff00, /* dirty by user */ 386 ENH_ALL_DIRTY = 0xffff /* all dirty */ 387 388 }; 389 390 struct disp_enhance_config { 391 struct disp_enhance_info info; 392 enum disp_enhance_dirty_flags flags; 393 }; 394 395 enum disp_smbl_dirty_flags { 396 SMBL_DIRTY_NONE = 0x00000000, 397 SMBL_DIRTY_ENABLE = 0x00000001, 398 SMBL_DIRTY_WINDOW = 0x00000002, 399 SMBL_DIRTY_SIZE = 0x00000004, 400 SMBL_DIRTY_BL = 0x00000008, 401 SMBL_DIRTY_ALL = 0x0000000F, 402 }; 403 404 struct disp_smbl_info { 405 struct disp_rect window; 406 u32 enable; 407 struct disp_rect size; 408 u32 backlight; 409 u32 backlight_dimming; 410 enum disp_smbl_dirty_flags flags; 411 }; 412 413 struct disp_csc_config { 414 u32 in_fmt; 415 u32 in_mode; 416 u32 in_color_range; 417 u32 out_fmt; 418 u32 out_mode; 419 u32 out_color_range; 420 u32 brightness; 421 u32 contrast; 422 u32 saturation; 423 u32 hue; 424 u32 enhance_mode; 425 u32 color; 426 u32 in_eotf; 427 u32 out_eotf; 428 }; 429 430 enum { 431 DE_RGB = 0, 432 DE_YUV = 1, 433 }; 434 435 enum disp_capture_dirty_flags { 436 CAPTURE_DIRTY_ADDRESS = 0x00000001, 437 CAPTURE_DIRTY_WINDOW = 0x00000002, 438 CAPTURE_DIRTY_SIZE = 0x00000004, 439 CAPTURE_DIRTY_ALL = 0x00000007, 440 }; 441 /* disp_s_frame_inner - display simple frame buffer 442 * 443 * @format: pixel format of fb 444 * @size: size for each plane 445 * @crop: crop zone to be fill image data 446 * @fd: dma_buf fd 447 * @addr: buffer addr for each plane 448 */ 449 struct disp_s_frame_inner { 450 enum disp_pixel_format format; 451 struct disp_rectsz size[3]; 452 struct disp_rect crop; 453 unsigned long long addr[3]; 454 int fd; 455 }; 456 457 /* disp_capture_info_inner - display capture information 458 * 459 * @window: the rectange on the screen to be capture 460 * @out_frame: the framebuffer to be restore capture image data 461 */ 462 struct disp_capture_info_inner { 463 struct disp_rect window; 464 struct disp_s_frame_inner out_frame; 465 }; 466 /* disp_capture_config - configuration for capture function 467 * 468 * @in_frame: input frame information 469 * @out_frame: output framebuffer infomation 470 * @disp: indicate which disp channel to be capture 471 * @flags: caputre flags 472 */ 473 struct disp_capture_config { 474 struct disp_s_frame in_frame; /* only format/size/crop valid */ 475 struct disp_s_frame out_frame; 476 u32 disp; /* which disp channel to be capture */ 477 enum disp_capture_dirty_flags flags; 478 }; 479 480 enum disp_lcd_if { 481 LCD_IF_HV = 0, 482 LCD_IF_CPU = 1, 483 LCD_IF_LVDS = 3, 484 LCD_IF_DSI = 4, 485 LCD_IF_EDP = 5, 486 LCD_IF_EXT_DSI = 6, 487 LCD_IF_VDPO = 7, 488 }; 489 490 enum disp_lcd_hv_if { 491 LCD_HV_IF_PRGB_1CYC = 0, /* parallel hv */ 492 LCD_HV_IF_SRGB_3CYC = 8, /* serial hv */ 493 LCD_HV_IF_DRGB_4CYC = 10, /* Dummy RGB */ 494 LCD_HV_IF_RGBD_4CYC = 11, /* RGB Dummy */ 495 LCD_HV_IF_CCIR656_2CYC = 12, 496 }; 497 498 enum disp_lcd_hv_srgb_seq { 499 LCD_HV_SRGB_SEQ_RGB_RGB = 0, 500 LCD_HV_SRGB_SEQ_RGB_BRG = 1, 501 LCD_HV_SRGB_SEQ_RGB_GBR = 2, 502 LCD_HV_SRGB_SEQ_BRG_RGB = 4, 503 LCD_HV_SRGB_SEQ_BRG_BRG = 5, 504 LCD_HV_SRGB_SEQ_BRG_GBR = 6, 505 LCD_HV_SRGB_SEQ_GRB_RGB = 8, 506 LCD_HV_SRGB_SEQ_GRB_BRG = 9, 507 LCD_HV_SRGB_SEQ_GRB_GBR = 10, 508 }; 509 510 enum disp_lcd_hv_syuv_seq { 511 LCD_HV_SYUV_SEQ_YUYV = 0, 512 LCD_HV_SYUV_SEQ_YVYU = 1, 513 LCD_HV_SYUV_SEQ_UYUV = 2, 514 LCD_HV_SYUV_SEQ_VYUY = 3, 515 }; 516 517 enum disp_lcd_hv_syuv_fdly { 518 LCD_HV_SYUV_FDLY_0LINE = 0, 519 LCD_HV_SRGB_FDLY_2LINE = 1, /* ccir ntsc */ 520 LCD_HV_SRGB_FDLY_3LINE = 2, /* ccir pal */ 521 }; 522 523 enum disp_lcd_cpu_if { 524 LCD_CPU_IF_RGB666_18PIN = 0, 525 LCD_CPU_IF_RGB666_9PIN = 10, 526 LCD_CPU_IF_RGB666_6PIN = 12, 527 LCD_CPU_IF_RGB565_16PIN = 8, 528 LCD_CPU_IF_RGB565_8PIN = 14, 529 }; 530 531 enum disp_lcd_cpu_mode { 532 LCD_CPU_AUTO_MODE = 0, 533 LCD_CPU_TRIGGER_MODE = 1, 534 }; 535 536 enum disp_lcd_te { 537 LCD_TE_DISABLE = 0, 538 LCD_TE_RISING = 1, 539 LCD_TE_FALLING = 2, 540 }; 541 542 enum disp_lcd_lvds_if { 543 LCD_LVDS_IF_SINGLE_LINK = 0, 544 LCD_LVDS_IF_DUAL_LINK = 1, 545 LCD_LVDS_IF_DUAL_LINK_SAME_SRC = 2, 546 }; 547 548 enum disp_lcd_lvds_colordepth { 549 LCD_LVDS_8bit = 0, 550 LCD_LVDS_6bit = 1, 551 }; 552 553 enum disp_lcd_lvds_mode { 554 LCD_LVDS_MODE_NS = 0, 555 LCD_LVDS_MODE_JEIDA = 1, 556 }; 557 558 enum disp_lcd_dsi_if { 559 LCD_DSI_IF_VIDEO_MODE = 0, 560 LCD_DSI_IF_COMMAND_MODE = 1, 561 LCD_DSI_IF_BURST_MODE = 2, 562 }; 563 564 enum disp_lcd_dsi_lane { 565 LCD_DSI_1LANE = 1, 566 LCD_DSI_2LANE = 2, 567 LCD_DSI_3LANE = 3, 568 LCD_DSI_4LANE = 4, 569 }; 570 571 enum disp_lcd_dsi_format { 572 LCD_DSI_FORMAT_RGB888 = 0, 573 LCD_DSI_FORMAT_RGB666 = 1, 574 LCD_DSI_FORMAT_RGB666P = 2, 575 LCD_DSI_FORMAT_RGB565 = 3, 576 }; 577 578 enum disp_lcd_frm { 579 LCD_FRM_BYPASS = 0, 580 LCD_FRM_RGB666 = 1, 581 LCD_FRM_RGB565 = 2, 582 }; 583 584 enum disp_lcd_cmap_color { 585 LCD_CMAP_B0 = 0x0, 586 LCD_CMAP_G0 = 0x1, 587 LCD_CMAP_R0 = 0x2, 588 LCD_CMAP_B1 = 0x4, 589 LCD_CMAP_G1 = 0x5, 590 LCD_CMAP_R1 = 0x6, 591 LCD_CMAP_B2 = 0x8, 592 LCD_CMAP_G2 = 0x9, 593 LCD_CMAP_R2 = 0xa, 594 LCD_CMAP_B3 = 0xc, 595 LCD_CMAP_G3 = 0xd, 596 LCD_CMAP_R3 = 0xe, 597 }; 598 599 struct __disp_dsi_dphy_timing_t { 600 unsigned int lp_clk_div; 601 unsigned int hs_prepare; 602 unsigned int hs_trail; 603 unsigned int clk_prepare; 604 unsigned int clk_zero; 605 unsigned int clk_pre; 606 unsigned int clk_post; 607 unsigned int clk_trail; 608 unsigned int hs_dly_mode; 609 unsigned int hs_dly; 610 unsigned int lptx_ulps_exit; 611 unsigned int hstx_ana0; 612 unsigned int hstx_ana1; 613 }; 614 615 /** 616 * lcd tcon mode(dual tcon drive dual dsi) 617 */ 618 enum disp_lcd_tcon_mode { 619 DISP_TCON_NORMAL_MODE = 0, 620 DISP_TCON_MASTER_SYNC_AT_FIRST_TIME, 621 DISP_TCON_MASTER_SYNC_EVERY_FRAME, 622 DISP_TCON_SLAVE_MODE, 623 DISP_TCON_DUAL_DSI, 624 }; 625 626 enum disp_lcd_dsi_port { 627 DISP_LCD_DSI_SINGLE_PORT = 0, 628 DISP_LCD_DSI_DUAL_PORT, 629 }; 630 631 struct disp_lcd_esd_info { 632 /*1:reset all module include tcon; 0:reset panel only*/ 633 unsigned char level; 634 /*unit:frame*/ 635 unsigned short freq; 636 /*1:in disp isr; 0:in reflush work*/ 637 unsigned char esd_check_func_pos; 638 /*count*/ 639 unsigned int cnt; 640 /*reset count*/ 641 unsigned int rst_cnt; 642 }; 643 644 struct disp_panel_para { 645 enum disp_lcd_if lcd_if; 646 647 enum disp_lcd_hv_if lcd_hv_if; 648 enum disp_lcd_hv_srgb_seq lcd_hv_srgb_seq; 649 enum disp_lcd_hv_syuv_seq lcd_hv_syuv_seq; 650 enum disp_lcd_hv_syuv_fdly lcd_hv_syuv_fdly; 651 652 enum disp_lcd_lvds_if lcd_lvds_if; 653 enum disp_lcd_lvds_colordepth lcd_lvds_colordepth; 654 enum disp_lcd_lvds_mode lcd_lvds_mode; 655 unsigned int lcd_lvds_io_polarity; 656 657 enum disp_lcd_cpu_if lcd_cpu_if; 658 enum disp_lcd_te lcd_cpu_te; 659 enum disp_lcd_dsi_port lcd_dsi_port_num; 660 enum disp_lcd_tcon_mode lcd_tcon_mode; 661 unsigned int lcd_slave_stop_pos; 662 unsigned int lcd_sync_pixel_num; 663 unsigned int lcd_sync_line_num; 664 unsigned int lcd_slave_tcon_num; 665 enum disp_lcd_cpu_mode lcd_cpu_mode; 666 667 enum disp_lcd_dsi_if lcd_dsi_if; 668 enum disp_lcd_dsi_lane lcd_dsi_lane; 669 enum disp_lcd_dsi_format lcd_dsi_format; 670 unsigned int lcd_dsi_eotp; 671 unsigned int lcd_dsi_vc; 672 enum disp_lcd_te lcd_dsi_te; 673 674 unsigned int lcd_tcon_en_odd_even; 675 676 unsigned int lcd_dsi_dphy_timing_en; 677 struct __disp_dsi_dphy_timing_t *lcd_dsi_dphy_timing_p; 678 679 unsigned int lcd_fsync_en; 680 unsigned int lcd_fsync_act_time; 681 unsigned int lcd_fsync_dis_time; 682 unsigned int lcd_fsync_pol; 683 684 unsigned int lcd_dclk_freq; 685 unsigned int lcd_x; /* horizontal resolution */ 686 unsigned int lcd_y; /* vertical resolution */ 687 unsigned int lcd_width; /* width of lcd in mm */ 688 unsigned int lcd_height; /* height of lcd in mm */ 689 unsigned int lcd_xtal_freq; 690 691 unsigned int lcd_pwm_used; 692 unsigned int lcd_pwm_ch; 693 unsigned int lcd_pwm_freq; 694 unsigned int lcd_pwm_pol; 695 696 unsigned int lcd_rb_swap; 697 unsigned int lcd_rgb_endian; 698 699 unsigned int lcd_vt; 700 unsigned int lcd_ht; 701 unsigned int lcd_vbp; 702 unsigned int lcd_hbp; 703 unsigned int lcd_vspw; 704 unsigned int lcd_hspw; 705 706 unsigned int lcd_interlace; 707 unsigned int lcd_hv_clk_phase; 708 unsigned int lcd_hv_sync_polarity; 709 unsigned int lcd_de_polarity; 710 711 unsigned int lcd_frm; 712 unsigned int lcd_gamma_en; 713 unsigned int lcd_cmap_en; 714 unsigned int lcd_bright_curve_en; 715 716 char lcd_size[8]; /* e.g. 7.9, 9.7 */ 717 char lcd_model_name[32]; 718 char lcd_driver_name[32]; 719 720 unsigned int tcon_index; /* not need to config for user */ 721 unsigned int lcd_fresh_mode; /* not need to config for user */ 722 unsigned int lcd_dclk_freq_original;/* not need to config for user */ 723 unsigned int ccir_clk_div;/*not need to config for user*/ 724 unsigned int input_csc;/*not need to config for user*/ 725 unsigned int lcd_gsensor_detect; 726 unsigned int lcd_hv_data_polarity; 727 728 }; 729 730 enum disp_mod_id { 731 DISP_MOD_DE = 0, 732 #if defined(CONFIG_ARCH_SUN50IW10) 733 DISP_MOD_DE1, 734 #endif 735 DISP_MOD_DEVICE, /* for timing controller common module */ 736 #if defined(CONFIG_ARCH_SUN50IW10) 737 DISP_MOD_DEVICE1, 738 #endif 739 DISP_MOD_LCD0, 740 DISP_MOD_LCD1, 741 DISP_MOD_LCD2, 742 DISP_MOD_LCD3, 743 DISP_MOD_DSI0, 744 DISP_MOD_DSI1, 745 DISP_MOD_DSI2, 746 DISP_MOD_DSI3, 747 DISP_MOD_HDMI, 748 DISP_MOD_LVDS, 749 DISP_MOD_EINK, 750 DISP_MOD_EDMA, 751 DISP_MOD_VDPO, 752 #if defined(CONFIG_ARCH_SUN50IW10) 753 DISP_MOD_DPSS0, 754 DISP_MOD_DPSS1, 755 #endif 756 DISP_MOD_NUM, 757 }; 758 759 typedef enum { 760 DISP_NOT_UPDATE = 0, 761 DISP_NORMAL_UPDATE = 1, 762 DISP_SMOOTH_UPDATE = 2, 763 } disp_config_update_t; 764 765 766 struct disp_bootloader_info { 767 int sync; /* 1: sync width bootloader */ 768 int disp; /* output disp at bootloader period */ 769 int type; /* output type at bootloader period */ 770 int mode; /* output mode at bootloader period */ 771 int format;/* YUV or RGB */ 772 int bits; /* color deep */ 773 int eotf; 774 int cs; /* color space */ 775 enum disp_dvi_hdmi dvi_hdmi; 776 enum disp_color_range range; 777 enum disp_scan_info scan; 778 unsigned int aspect_ratio; 779 780 }; 781 782 #define DEBUG_TIME_SIZE 100 783 struct disp_health_info { 784 unsigned long sync_time[DEBUG_TIME_SIZE]; /* for_debug */ 785 unsigned int sync_time_index; /* for_debug */ 786 unsigned int skip_cnt; 787 unsigned int skip_cnt_timeout; 788 unsigned int error_cnt; /* under flow .ect */ 789 unsigned long long irq_cnt; 790 unsigned int vsync_cnt; 791 unsigned int vsync_skip_cnt; 792 }; 793 794 struct disp_bsp_init_para { 795 uintptr_t reg_base[DISP_MOD_NUM]; 796 u32 irq_no[DISP_MOD_NUM]; 797 disp_clk_t clk_de[DE_NUM]; 798 disp_clk_t clk_bus_de[DE_NUM]; 799 disp_clk_t clk_bus_dpss_top[DISP_DEVICE_NUM]; 800 disp_clk_t clk_tcon_lcd[DISP_DEVICE_NUM]; 801 disp_clk_t clk_bus_tcon_lcd[DISP_DEVICE_NUM]; 802 disp_clk_t clk_mipi_dsi[CLK_DSI_NUM]; 803 disp_clk_t clk_bus_mipi_dsi[CLK_DSI_NUM]; 804 struct reset_control *rst_bus_lvds; 805 s32 (*disp_int_process)(u32 sel); 806 s32 (*vsync_event)(u32 sel); 807 s32 (*start_process)(void); 808 s32 (*capture_event)(u32 sel); 809 s32 (*shadow_protect)(u32 sel, bool protect); 810 struct disp_bootloader_info boot_info; 811 }; 812 813 typedef void (*LCD_FUNC) (u32 sel); 814 struct disp_lcd_function { 815 LCD_FUNC func; 816 unsigned int delay; /* ms */ 817 }; 818 819 #define LCD_MAX_SEQUENCES 7 820 struct disp_lcd_flow { 821 struct disp_lcd_function func[LCD_MAX_SEQUENCES]; 822 unsigned int func_num; 823 unsigned int cur_step; 824 }; 825 826 struct disp_lcd_panel_fun { 827 void (*cfg_panel_info)(struct panel_extend_para *info); 828 s32 (*cfg_open_flow)(u32 sel); 829 s32 (*cfg_close_flow)(u32 sel); 830 s32 (*lcd_user_defined_func)(u32 sel, u32 para1, 831 u32 para2, u32 para3); 832 s32 (*set_bright)(u32 sel, u32 bright); 833 /*check if panel is ok.return 0 if ok*/ 834 s32 (*esd_check)(u32 sel); 835 /*reset panel flow*/ 836 s32 (*reset_panel)(u32 sel); 837 /*see the definition of struct disp_lcd_esd_info */ 838 s32 (*set_esd_info)(struct disp_lcd_esd_info *p_info); 839 }; 840 841 struct disp_enhance_para { 842 /* basic adjust */ 843 u32 bright; 844 u32 contrast; 845 u32 saturation; 846 u32 hue; 847 u32 mode; 848 /* ehnance */ 849 u32 sharp; /* 0-off; 1~3-on. */ 850 u32 auto_contrast; /* 0-off; 1~3-on. */ 851 u32 auto_color; /* 0-off; 1-on. */ 852 u32 fancycolor_red; /* 0-Off; 1-2-on. */ 853 u32 fancycolor_green; /* 0-Off; 1-2-on. */ 854 u32 fancycolor_blue; /* 0-Off; 1-2-on. */ 855 struct disp_rect window; 856 u32 enable; 857 }; 858 859 struct disp_device { 860 struct list_head list; 861 /* data fields */ 862 char name[32]; 863 u32 disp; 864 /* indicate the index of hw device(timing controller) */ 865 u32 hwdev_index; 866 u32 fix_timing; 867 enum disp_output_type type; 868 struct disp_manager *manager; 869 struct disp_video_timings timings; 870 hal_work close_eink_panel_work; 871 void *priv_data; 872 873 /* function fileds */ 874 /* init: script init && clock init && pwm init && register irq 875 * exit: clock exit && unregister irq 876 */ 877 s32 (*init)(struct disp_device *dispdev); 878 s32 (*exit)(struct disp_device *dispdev); 879 880 s32 (*set_manager)(struct disp_device *dispdev, 881 struct disp_manager *mgr); 882 s32 (*unset_manager)(struct disp_device *dispdev); 883 884 s32 (*enable)(struct disp_device *dispdev); 885 s32 (*fake_enable)(struct disp_device *dispdev); 886 s32 (*sw_enable)(struct disp_device *dispdev); 887 s32 (*disable)(struct disp_device *dispdev); 888 s32 (*is_enabled)(struct disp_device *dispdev); 889 s32 (*check_if_enabled)(struct disp_device *dispdev); 890 s32 (*is_used)(struct disp_device *dispdev); 891 s32 (*get_resolution)(struct disp_device *dispdev, u32 *xres, 892 u32 *yres); 893 s32 (*get_dimensions)(struct disp_device *dispdev, u32 *width, 894 u32 *height); 895 s32 (*set_timings)(struct disp_device *dispdev, 896 struct disp_video_timings *timings); 897 s32 (*get_timings)(struct disp_device *dispdev, 898 struct disp_video_timings *timings); 899 s32 (*check_timings)(struct disp_device *dispdev, 900 struct disp_video_timings *timings); 901 s32 (*smooth_enable)(struct disp_device *dispdev); 902 s32 (*detect)(struct disp_device *dispdev); 903 s32 (*set_detect)(struct disp_device *dispdev, bool hpd); 904 s32 (*get_status)(struct disp_device *dispdev); 905 s32 (*get_fps)(struct disp_device *dispdev); 906 /* 907 * check if be in the safe period now, 908 * safe period means the current line is less than the start_delay 909 */ 910 bool (*is_in_safe_period)(struct disp_device *dispdev); 911 u32 (*usec_before_vblank)(struct disp_device *dispdev); 912 913 s32 (*get_input_csc)(struct disp_device *dispdev); 914 s32 (*get_input_color_range)(struct disp_device *dispdev); 915 s32 (*is_interlace)(struct disp_device *dispdev); 916 917 /* power manager */ 918 s32 (*early_suspend)(struct disp_device *dispdev); 919 s32 (*late_resume)(struct disp_device *dispdev); 920 s32 (*suspend)(struct disp_device *dispdev); 921 s32 (*resume)(struct disp_device *dispdev); 922 923 s32 (*dump)(struct disp_device *dispdev, char *buf); 924 925 /* HDMI /TV */ 926 s32 (*set_mode)(struct disp_device *dispdev, u32 mode); 927 s32 (*get_mode)(struct disp_device *dispdev); 928 s32 (*set_static_config)(struct disp_device *dispdev, 929 struct disp_device_config *config); 930 s32 (*get_static_config)(struct disp_device *dispdev, 931 struct disp_device_config *config); 932 s32 (*set_dynamic_config)(struct disp_device *dispdev, 933 struct disp_device_dynamic_config *config); 934 s32 (*get_dynamic_config)(struct disp_device *dispdev, 935 struct disp_device_dynamic_config *config); 936 937 s32 (*cec_standby_request)(struct disp_device *dispdev); 938 s32 (*cec_send_one_touch_play)(struct disp_device *dispdev); 939 /* 940 * check_config_dirty 941 * check if the config is not the same with current one 942 */ 943 disp_config_update_t (*check_config_dirty)(struct disp_device *dispdev, 944 struct disp_device_config *config); 945 s32 (*check_support_mode)(struct disp_device *dispdev, u32 mode); 946 s32 (*set_func)(struct disp_device *dispdev, 947 struct disp_device_func *func); 948 s32 (*set_tv_func)(struct disp_device *dispdev, 949 struct disp_tv_func *func); 950 s32 (*set_enhance_mode)(struct disp_device *dispdev, u32 mode); 951 952 /* LCD */ 953 s32 (*set_bright)(struct disp_device *dispdev, u32 bright); 954 s32 (*get_bright)(struct disp_device *dispdev); 955 s32 (*backlight_enable)(struct disp_device *dispdev); 956 s32 (*backlight_disable)(struct disp_device *dispdev); 957 s32 (*pwm_enable)(struct disp_device *dispdev); 958 s32 (*pwm_disable)(struct disp_device *dispdev); 959 s32 (*power_enable)(struct disp_device *dispdev, u32 power_id); 960 s32 (*power_disable)(struct disp_device *dispdev, u32 power_id); 961 s32 (*tcon_enable)(struct disp_device *dispdev); 962 s32 (*tcon_disable)(struct disp_device *dispdev); 963 s32 (*set_bright_dimming)(struct disp_device *dispdev, u32 dimming); 964 965 struct disp_lcd_flow *(*get_open_flow)(struct disp_device *dispdev); 966 struct disp_lcd_flow *(*get_close_flow)(struct disp_device *dispdev); 967 s32 (*pin_cfg)(struct disp_device *dispdev, u32 bon); 968 s32 (*set_gamma_tbl)(struct disp_device *dispdev, u32 *tbl, 969 u32 size); 970 s32 (*enable_gamma)(struct disp_device *dispdev); 971 s32 (*disable_gamma)(struct disp_device *dispdev); 972 s32 (*set_color_temperature)(struct disp_device *dispdev, s32 color_temperature); 973 s32 (*get_color_temperature)(struct disp_device *dispdev); 974 s32 (*set_panel_func)(struct disp_device *lcd, char *name, 975 struct disp_lcd_panel_fun *lcd_cfg); 976 s32 (*set_open_func)(struct disp_device *lcd, LCD_FUNC func, 977 u32 delay); 978 s32 (*set_close_func)(struct disp_device *lcd, LCD_FUNC func, 979 u32 delay); 980 s32 (*gpio_set_value)(struct disp_device *dispdev, 981 u32 io_index, u32 value); 982 s32 (*gpio_set_direction)(struct disp_device *dispdev, 983 u32 io_index, u32 direction); 984 s32 (*get_panel_info)(struct disp_device *dispdev, 985 struct disp_panel_para *info); 986 void (*show_builtin_patten)(struct disp_device *dispdev, u32 patten); 987 }; 988 989 /* manager */ 990 struct disp_manager { 991 /* data fields */ 992 char name[32]; 993 u32 disp; 994 u32 num_chns; 995 u32 num_layers; 996 struct disp_device *device; 997 struct disp_smbl *smbl; 998 struct disp_enhance *enhance; 999 struct disp_capture *cptr; 1000 1001 struct list_head lyr_list; 1002 #if defined(CONFIG_SUNXI_DISP2_FB_ROTATION_SUPPORT) 1003 struct disp_rotation_sw *rot_sw; 1004 #endif 1005 1006 #ifdef SUPPORT_WB 1007 wait_queue_head_t write_back_queue; 1008 u32 write_back_finish; 1009 #endif 1010 1011 /* function fields */ 1012 s32 (*enable)(struct disp_manager *mgr); 1013 s32 (*sw_enable)(struct disp_manager *mgr); 1014 s32 (*disable)(struct disp_manager *mgr); 1015 s32 (*is_enabled)(struct disp_manager *mgr); 1016 s32 (*blank)(struct disp_manager *mgr, bool blank); 1017 1018 /* init: clock init && reg init && register irq 1019 * exit: clock exit && unregister irq 1020 */ 1021 s32 (*init)(struct disp_manager *mgr); 1022 s32 (*exit)(struct disp_manager *mgr); 1023 1024 s32 (*set_back_color)(struct disp_manager *mgr, 1025 struct disp_color *bk_color); 1026 s32 (*get_back_color)(struct disp_manager *mgr, 1027 struct disp_color *bk_color); 1028 s32 (*set_color_key)(struct disp_manager *mgr, 1029 struct disp_colorkey *ck); 1030 s32 (*get_color_key)(struct disp_manager *mgr, 1031 struct disp_colorkey *ck); 1032 1033 s32 (*get_screen_size)(struct disp_manager *mgr, u32 *width, 1034 u32 *height); 1035 s32 (*set_screen_size)(struct disp_manager *mgr, u32 width, 1036 u32 height); 1037 s32 (*get_clk_rate)(struct disp_manager *mgr); 1038 1039 /* layer mamage */ 1040 s32 (*check_layer_zorder)(struct disp_manager *mgr, 1041 struct disp_layer_config *config, 1042 u32 layer_num); 1043 s32 (*set_layer_config)(struct disp_manager *mgr, 1044 struct disp_layer_config *config, 1045 unsigned int layer_num); 1046 s32 (*get_layer_config)(struct disp_manager *mgr, 1047 struct disp_layer_config *config, 1048 unsigned int layer_num); 1049 s32 (*set_layer_config2)(struct disp_manager *mgr, 1050 struct disp_layer_config2 *config, 1051 unsigned int layer_num); 1052 s32 (*get_layer_config2)(struct disp_manager *mgr, 1053 struct disp_layer_config2 *config, 1054 unsigned int layer_num); 1055 s32 (*force_set_layer_config)(struct disp_manager *mgr, struct disp_layer_config *config, unsigned int layer_num); 1056 s32 (*force_set_layer_config_exit)(struct disp_manager *mgr); 1057 s32 (*extend_layer_config)(struct disp_manager *mgr, 1058 struct disp_layer_config *info, 1059 unsigned int layer_num); 1060 s32 (*set_output_color_range)(struct disp_manager *mgr, 1061 u32 color_range); 1062 s32 (*get_output_color_range)(struct disp_manager *mgr); 1063 s32 (*update_color_space)(struct disp_manager *mgr); 1064 s32 (*smooth_switch)(struct disp_manager *mgr); 1065 s32 (*set_palette)(struct disp_manager *mgr, struct disp_palette_config *config); 1066 s32 (*apply)(struct disp_manager *mgr); 1067 s32 (*force_apply)(struct disp_manager *mgr); 1068 s32 (*update_regs)(struct disp_manager *mgr); 1069 s32 (*sync)(struct disp_manager *mgr, bool sync); 1070 s32 (*tasklet)(struct disp_manager *mgr); 1071 1072 /* debug interface, dump manager info */ 1073 s32 (*dump)(struct disp_manager *mgr); 1074 }; 1075 1076 struct disp_layer { 1077 /* data fields */ 1078 char name[32]; 1079 u32 disp; 1080 u32 chn; 1081 u32 id; 1082 1083 /* enum disp_layer_feat caps; */ 1084 struct disp_manager *manager; 1085 struct list_head list; 1086 void *data; 1087 1088 /* function fileds */ 1089 s32 (*is_support_format)(struct disp_layer *layer, 1090 enum disp_pixel_format fmt); 1091 s32 (*set_manager)(struct disp_layer *layer, 1092 struct disp_manager *mgr); 1093 s32 (*unset_manager)(struct disp_layer *layer); 1094 s32 (*check)(struct disp_layer *layer, 1095 struct disp_layer_config *config); 1096 s32 (*check2)(struct disp_layer *layer, 1097 struct disp_layer_config2 *config); 1098 s32 (*save_and_dirty_check)(struct disp_layer *layer, 1099 struct disp_layer_config *config); 1100 s32 (*save_and_dirty_check2)(struct disp_layer *layer, 1101 struct disp_layer_config2 *config); 1102 s32 (*get_config)(struct disp_layer *layer, 1103 struct disp_layer_config *config); 1104 s32 (*get_config2)(struct disp_layer *layer, 1105 struct disp_layer_config2 *config); 1106 s32 (*apply)(struct disp_layer *layer); 1107 s32 (*force_apply)(struct disp_layer *layer); 1108 s32 (*is_dirty)(struct disp_layer *layer); 1109 s32 (*dirty_clear)(struct disp_layer *layer); 1110 /* init: NULL 1111 * exit: NULL 1112 */ 1113 s32 (*init)(struct disp_layer *layer); 1114 s32 (*exit)(struct disp_layer *layer); 1115 s32 (*get_frame_id)(struct disp_layer *layer); 1116 s32 (*dump)(struct disp_layer *layer); 1117 }; 1118 1119 struct disp_smbl { 1120 /* static fields */ 1121 char *name; 1122 u32 disp; 1123 u32 backlight; 1124 struct disp_manager *manager; 1125 1126 /* 1127 * The following functions do not block: 1128 * 1129 * is_enabled 1130 * set_layer_info 1131 * get_layer_info 1132 * 1133 * The rest of the functions may block and cannot be called from 1134 * interrupt context 1135 */ 1136 1137 s32 (*enable)(struct disp_smbl *smbl); 1138 s32 (*disable)(struct disp_smbl *smbl); 1139 bool (*is_enabled)(struct disp_smbl *smbl); 1140 s32 (*set_manager)(struct disp_smbl *smbl, struct disp_manager *mgr); 1141 s32 (*unset_manager)(struct disp_smbl *smbl); 1142 s32 (*update_backlight)(struct disp_smbl *smbl, unsigned int bl); 1143 1144 /* init: NULL 1145 * exit: NULL 1146 */ 1147 s32 (*init)(struct disp_smbl *smbl); 1148 s32 (*exit)(struct disp_smbl *smbl); 1149 1150 s32 (*apply)(struct disp_smbl *smbl); 1151 s32 (*update_regs)(struct disp_smbl *smbl); 1152 s32 (*force_apply)(struct disp_smbl *smbl); 1153 s32 (*sync)(struct disp_smbl *smbl); 1154 s32 (*tasklet)(struct disp_smbl *smbl); 1155 1156 s32 (*set_window)(struct disp_smbl *smbl, struct disp_rect *window); 1157 s32 (*get_window)(struct disp_smbl *smbl, struct disp_rect *window); 1158 s32 (*dump)(struct disp_smbl *smbl, char *buf); 1159 }; 1160 1161 struct disp_enhance { 1162 /* static fields */ 1163 char *name; 1164 u32 disp; 1165 struct disp_manager *manager; 1166 1167 /* 1168 * The following functions do not block: 1169 * 1170 * is_enabled 1171 * set_layer_info 1172 * get_layer_info 1173 * 1174 * The rest of the functions may block and cannot be called from 1175 * interrupt context 1176 */ 1177 1178 s32 (*enable)(struct disp_enhance *enhance); 1179 s32 (*disable)(struct disp_enhance *enhance); 1180 bool (*is_enabled)(struct disp_enhance *enhance); 1181 s32 (*set_manager)(struct disp_enhance *enhance, 1182 struct disp_manager *mgr); 1183 s32 (*unset_manager)(struct disp_enhance *enhance); 1184 1185 /* init: NULL 1186 * exit: NULL 1187 */ 1188 s32 (*init)(struct disp_enhance *enhance); 1189 s32 (*exit)(struct disp_enhance *enhance); 1190 1191 s32 (*apply)(struct disp_enhance *enhance); 1192 s32 (*update_regs)(struct disp_enhance *enhance); 1193 s32 (*force_apply)(struct disp_enhance *enhance); 1194 s32 (*sync)(struct disp_enhance *enhance); 1195 s32 (*tasklet)(struct disp_enhance *enhance); 1196 1197 /* power manager */ 1198 s32 (*early_suspend)(struct disp_enhance *enhance); 1199 s32 (*late_resume)(struct disp_enhance *enhance); 1200 s32 (*suspend)(struct disp_enhance *enhance); 1201 s32 (*resume)(struct disp_enhance *enhance); 1202 1203 s32 (*set_bright)(struct disp_enhance *enhance, u32 val); 1204 s32 (*set_saturation)(struct disp_enhance *enhance, u32 val); 1205 s32 (*set_contrast)(struct disp_enhance *enhance, u32 val); 1206 s32 (*set_hue)(struct disp_enhance *enhance, u32 val); 1207 s32 (*set_edge)(struct disp_enhance *enhance, u32 val); 1208 s32 (*set_detail)(struct disp_enhance *enhance, u32 val); 1209 s32 (*set_denoise)(struct disp_enhance *enhance, u32 val); 1210 s32 (*set_mode)(struct disp_enhance *enhance, u32 val); 1211 s32 (*set_window)(struct disp_enhance *enhance, 1212 struct disp_rect *window); 1213 s32 (*get_bright)(struct disp_enhance *enhance); 1214 s32 (*get_saturation)(struct disp_enhance *enhance); 1215 s32 (*get_contrast)(struct disp_enhance *enhance); 1216 s32 (*get_hue)(struct disp_enhance *enhance); 1217 s32 (*get_edge)(struct disp_enhance *enhance); 1218 s32 (*get_detail)(struct disp_enhance *enhance); 1219 s32 (*get_denoise)(struct disp_enhance *enhance); 1220 s32 (*get_mode)(struct disp_enhance *enhance); 1221 s32 (*get_window)(struct disp_enhance *enhance, 1222 struct disp_rect *window); 1223 s32 (*set_para)(struct disp_enhance *enhance, 1224 struct disp_enhance_para *para); 1225 s32 (*demo_enable)(struct disp_enhance *enhance); 1226 s32 (*demo_disable)(struct disp_enhance *enhance); 1227 s32 (*dump)(struct disp_enhance *enhance, char *buf); 1228 }; 1229 1230 struct disp_capture { 1231 char name[16]; 1232 u32 disp; 1233 struct disp_manager *manager; 1234 1235 s32 (*set_manager)(struct disp_capture *cptr, 1236 struct disp_manager *mgr); 1237 s32 (*unset_manager)(struct disp_capture *cptr); 1238 s32 (*start)(struct disp_capture *cptr); 1239 s32 (*commmit)(struct disp_capture *cptr, 1240 struct disp_capture_info *info); 1241 s32 (*commmit2)(struct disp_capture *cptr, 1242 struct disp_capture_info2 *info); 1243 s32 (*stop)(struct disp_capture *cptr); 1244 s32 (*sync)(struct disp_capture *cptr); 1245 s32 (*tasklet)(struct disp_capture *cptr); 1246 s32 (*init)(struct disp_capture *cptr); 1247 s32 (*exit)(struct disp_capture *cptr); 1248 /* 0: finish, other: fail/err */ 1249 s32 (*query)(struct disp_capture *cptr); 1250 1251 /* debug interface, dump capture info */ 1252 s32 (*dump)(struct disp_capture *cptr, char *buf); 1253 /* inner interface */ 1254 s32 (*apply)(struct disp_capture *cptr); 1255 }; 1256 1257 #if defined(CONFIG_SUNXI_DISP2_FB_ROTATION_SUPPORT) 1258 struct disp_rotation_sw { 1259 u32 disp; 1260 u32 degree; 1261 struct disp_rectsz screen_size; /* virtual screen_size */ 1262 1263 struct disp_manager *manager; 1264 1265 s32 (*init)(struct disp_rotation_sw *rot_sw); 1266 s32 (*exit)(struct disp_rotation_sw *rot_sw); 1267 s32 (*set_layer_degree)(struct disp_rotation_sw *rot_sw, u32 chn, 1268 u32 lyr_id, u32 degree); 1269 s32 (*get_layer_degree)(struct disp_rotation_sw *rot_sw, u32 chn, 1270 u32 lyr_id); 1271 s32 (*set_manager)(struct disp_rotation_sw *rot_sw, 1272 struct disp_manager *mgr); 1273 s32 (*unset_manager)(struct disp_rotation_sw *rot_sw); 1274 s32 (*apply)(struct disp_rotation_sw *rot_sw, 1275 struct disp_layer_config *lyr_config, 1276 struct disp_rect src_dirty_rect); 1277 s32 (*checkout)(struct disp_rotation_sw *rot_sw, 1278 struct disp_layer_config *lyr_config); 1279 }; 1280 #endif 1281 1282 struct ee_img { 1283 unsigned long addr; 1284 unsigned int pitch; 1285 unsigned int w; /* image width */ 1286 unsigned int h; /* image height */ 1287 }; 1288 1289 struct rect_size { 1290 u32 width; 1291 u32 height; 1292 u32 align; 1293 }; 1294 1295 #if defined(CONFIG_EINK_PANEL_USED) 1296 struct area_info { 1297 unsigned int x_top; 1298 unsigned int y_top; 1299 unsigned int x_bottom; 1300 unsigned int y_bottom; 1301 }; 1302 1303 struct eink_timing_param { 1304 unsigned int lbl; /* */ 1305 unsigned int lel; /* */ 1306 unsigned int lsl; 1307 unsigned int fbl; /* */ 1308 unsigned int fel; /* */ 1309 unsigned int fsl; /* */ 1310 unsigned int width; /* image width */ 1311 unsigned int height; /* image height */ 1312 }; 1313 1314 enum eink_flash_mode { 1315 LOCAL, 1316 GLOBAL, 1317 INIT 1318 }; 1319 1320 enum buf_use_state { 1321 FREE, 1322 USED 1323 }; 1324 1325 enum eink_update_mode { 1326 /* GLOBAL */ 1327 EINK_INIT_MODE = 0x01, 1328 EINK_DU_MODE = 0x02, 1329 EINK_GC16_MODE = 0x04, 1330 EINK_A2_MODE = 0x10, 1331 EINK_GC16_LOCAL_MODE = 0x84, 1332 1333 /* LOCAL */ 1334 EINK_DU_RECT_MODE = 0x402, 1335 EINK_GC16_RECT_MODE = 0x404, 1336 EINK_A2_RECT_MODE = 0x410, 1337 EINK_GC16_LOCAL_RECT_MODE = 0x484, 1338 }; 1339 1340 struct eink_8bpp_image { 1341 enum eink_update_mode update_mode; 1342 enum eink_flash_mode flash_mode; 1343 enum buf_use_state state; 1344 void *vaddr; 1345 void *paddr; 1346 bool window_calc_enable; 1347 struct rect_size size; 1348 struct area_info update_area; 1349 }; 1350 1351 struct eink_init_param { 1352 bool used; 1353 u8 eink_moudule_type; 1354 u8 eink_version_type; 1355 u8 eink_ctrl_data_type; 1356 u8 eink_bits; /*0->3bits,1->4bits,2->5bits */ 1357 u8 eink_mode; /*0->8data,1->16data */ 1358 struct eink_timing_param timing; 1359 char wavefile_path[32]; 1360 }; 1361 1362 enum eink_bit_num { 1363 EINK_BIT_1 = 0x01, 1364 EINK_BIT_2 = 0x02, 1365 EINK_BIT_3 = 0x03, 1366 EINK_BIT_4 = 0x04, 1367 EINK_BIT_5 = 0x05 1368 }; 1369 1370 /* #define EINK_FLUSH_TIME_TEST */ 1371 1372 struct disp_eink_manager { 1373 unsigned int disp; 1374 unsigned int test; 1375 int tcon_flag; 1376 int eink_panel_temperature; 1377 1378 unsigned int flush_continue_flag; 1379 struct tasklet_struct sync_tasklet; 1380 struct tasklet_struct decode_tasklet; 1381 wait_queue_head_t decode_taske_queue; 1382 struct work_struct decode_work; 1383 struct eink_private *private_data; 1384 struct disp_manager *mgr; 1385 struct eink_buffer_manager *buffer_mgr; 1386 struct pipeline_manager *pipeline_mgr; 1387 struct format_manager *convert_mgr; 1388 struct task_struct *detect_fresh_task; 1389 struct task_struct *debug_task; 1390 struct mutex standby_lock; 1391 int (*eink_update)(struct disp_eink_manager *manager, 1392 struct disp_layer_config_inner *config, 1393 unsigned int layer_num, 1394 enum eink_update_mode mode, 1395 struct area_info update_area); 1396 int (*enable)(struct disp_eink_manager *); 1397 int (*disable)(struct disp_eink_manager *); 1398 int (*op_skip)(struct disp_eink_manager *manager, u32 skip); 1399 int (*suspend)(struct disp_eink_manager *); 1400 int (*resume)(struct disp_eink_manager *); 1401 void (*clearwd)(struct disp_eink_manager *, int); 1402 /*for debug */ 1403 int (*decode)(struct disp_eink_manager *, int); 1404 int (*set_temperature)(struct disp_eink_manager *manager, 1405 unsigned int temp); 1406 unsigned int (*get_temperature)(struct disp_eink_manager *manager); 1407 }; 1408 1409 struct image_format { 1410 enum disp_pixel_format format; 1411 unsigned int width; 1412 unsigned int height; 1413 unsigned long addr1; 1414 unsigned long addr2; 1415 unsigned long addr3; 1416 }; 1417 1418 struct format_manager { 1419 unsigned int disp; 1420 unsigned int irq_num; 1421 unsigned int write_back_finish; 1422 wait_queue_head_t write_back_queue; 1423 struct clk *clk; 1424 int (*enable)(unsigned int id); 1425 int (*disable)(unsigned int id); 1426 int (*start_convert)(unsigned int id, 1427 struct disp_layer_config_inner *config, 1428 unsigned int layer_num, 1429 struct image_format *dest); 1430 }; 1431 #endif 1432 #endif 1433