1 /** 2 ********************************************************************************* 3 * 4 * @file ald_nor_lcd.h 5 * @brief Header file of EBI_NOR_LCD module driver 6 * 7 * @version V1.0 8 * @date 07 Dec 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 07 Dec 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_NOR_LCD_H_ 34 #define __ALD_NOR_LCD_H_ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "ald_ebi.h" 41 42 /** @addtogroup ES32FXXX_ALD 43 * @{ 44 */ 45 46 /** @addtogroup NOR_LCD 47 * @{ 48 */ 49 50 /** 51 * @defgroup NOR_LCD_Private_Constants NOR LCD Private Constants 52 * @{ 53 */ 54 55 /* NOR device IDs addresses */ 56 #define MC_ADDRESS ((uint16_t)0x0000U) 57 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U) 58 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU) 59 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU) 60 61 /* NOR CFI IDs addresses */ 62 #define CFI1_ADDRESS ((uint16_t)0x10U) 63 #define CFI2_ADDRESS ((uint16_t)0x11U) 64 #define CFI3_ADDRESS ((uint16_t)0x12U) 65 #define CFI4_ADDRESS ((uint16_t)0x13U) 66 67 /* NOR operation wait timeout */ 68 #define NOR_TMEOUT ((uint16_t)0xFFFFU) 69 70 /* NOR memory data width */ 71 #define NOR_MEMORY_8B ((uint8_t)0x0U) 72 #define NOR_MEMORY_16B ((uint8_t)0x1U) 73 74 /* NOR memory device read/write start address */ 75 #define NOR_MEMORY_ADRESS1 EBI_BANK1_1 76 #define NOR_MEMORY_ADRESS2 EBI_BANK1_2 77 #define NOR_MEMORY_ADRESS3 EBI_BANK1_3 78 #define NOR_MEMORY_ADRESS4 EBI_BANK1_4 79 80 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U 81 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U 82 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU 83 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U 84 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U 85 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU 86 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U 87 88 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U 89 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU 90 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055U 91 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U 92 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U 93 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U 94 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU 95 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U 96 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U 97 #define NOR_CMD_DATA_CFI (uint16_t)0x0098U 98 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U 99 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U 100 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U 101 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U 102 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U 103 /** 104 * @} 105 */ 106 107 /** @defgroup NOR_LCD_Private_Macros NOR_LCD Private Macros 108 * @{ 109 */ 110 #define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS) \ 111 ((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? \ 112 ((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))): \ 113 ((uint32_t)((NOR_ADDR) + (ADDRESS))))) 114 #define NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA)) 115 /** 116 * @} 117 */ 118 119 /** @defgroup NOR_LCD_Public_Types NOR_LCD Public Types 120 * @{ 121 */ 122 /** 123 * @brief ALD SRAM State structures definition 124 */ 125 typedef enum { 126 ALD_NOR_STATE_RESET = 0x00U, /**< NOR not yet initialized or disabled */ 127 ALD_NOR_STATE_READY = 0x01U, /**< NOR initialized and ready for use */ 128 ALD_NOR_STATE_BUSY = 0x02U, /**< NOR internal processing is ongoing */ 129 ALD_NOR_STATE_ERROR = 0x03U, /**< NOR error state */ 130 ALD_NOR_STATE_PROTECTED = 0x04U /**< NOR NORSRAM device write protected */ 131 } ald_nor_state_t; 132 133 /** 134 * @brief EBI NOR Status typedef 135 */ 136 typedef enum { 137 ALD_NOR_STATUS_SUCCESS = 0U, /**< NOR status success */ 138 ALD_NOR_STATUS_ONGOING, /**< NOR status ongoing */ 139 ALD_NOR_STATUS_ERROR, /**< NOR status error */ 140 ALD_NOR_STATUS_TIMEOUT, /**< NOR status timeout */ 141 } nor_status_t; 142 143 /** 144 * @brief EBI NOR ID typedef 145 */ 146 typedef struct { 147 uint16_t m_code; /**< Defines the device's manufacturer code used to identify the memory */ 148 uint16_t device_code1; /**< DEVICE_CODE1_ADDR code1 */ 149 uint16_t device_code2; /**< DEVICE_CODE1_ADDR code2 */ 150 uint16_t device_code3; /**< DEVICE_CODE1_ADDR code3 */ 151 } nor_id_t; 152 153 /** 154 * @brief EBI NOR CFI typedef 155 */ 156 typedef struct { 157 uint16_t cfi_1; /**< NOR CFI 1 */ 158 uint16_t cfi_2; /**< NOR CFI 2 */ 159 uint16_t cfi_3; /**< NOR CFI 3 */ 160 uint16_t cfi_4; /**< NOR CFI 4 */ 161 } nor_cfi_t; 162 163 /** 164 * @brief NOR handle Structure definition 165 */ 166 typedef struct { 167 EBI_NOR_SRAM_TypeDef *instance; /**< Register base address */ 168 EBI_NOR_SRAM_EXTENDED_TypeDef *ext; /**< Extended mode register base address */ 169 ald_ebi_nor_sram_init_t init; /**< NOR device control configuration parameters */ 170 lock_state_t lock; /**< NOR locking object */ 171 __IO ald_nor_state_t state; /**< NOR device access state */ 172 } nor_handle_t; 173 /** 174 * @} 175 */ 176 177 /** @addtogroup NOR_Public_Functions 178 * @{ 179 */ 180 /** @addtogroup NOR_Public_Functions_Group1 181 * @{ 182 */ 183 /* Initialization/de-initialization functions */ 184 ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing); 185 ald_status_t ald_nor_deinit(nor_handle_t *hperh); 186 /** 187 * @} 188 */ 189 /** @addtogroup NOR_LCD_Public_Functions_Group2 190 * @{ 191 */ 192 /* I/O operation functions */ 193 ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id); 194 ald_status_t ald_nor_return_readmode(nor_handle_t *hperh); 195 ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); 196 ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data); 197 ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); 198 ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size); 199 ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr); 200 ald_status_t ald_nor_erase_chip(nor_handle_t *hperh); 201 ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi); 202 /** 203 * @} 204 */ 205 /** @addtogroup NOR_LCD_Public_Functions_Group3 206 * @{ 207 */ 208 /* Control functions */ 209 ald_status_t ald_nor_write_enable(nor_handle_t *hperh); 210 ald_status_t ald_nor_write_disable(nor_handle_t *hperh); 211 /** 212 * @} 213 */ 214 /** @addtogroup NOR_LCD_Public_Functions_Group4 215 * @{ 216 */ 217 /* State functions */ 218 ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh); 219 nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout); 220 /** 221 * @} 222 */ 223 /** 224 * @} 225 */ 226 /** 227 * @} 228 */ 229 /** 230 * @} 231 */ 232 #ifdef __cplusplus 233 } 234 #endif 235 236 #endif /* __ALD_NOR_LCD_H__ */ 237