1 /**
2 * \file
3 *
4 * \brief SAM I2C Master Driver
5 *
6 * Copyright (C) 2012-2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 *
42 */
43 /*
44 * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
45 */
46
47 #include "i2c_master.h"
48
49 #if I2C_MASTER_CALLBACK_MODE == true
50 # include "i2c_master_interrupt.h"
51 #endif
52
53 /* Forward declaration */
54 enum status_code _i2c_master_wait_for_bus(
55 struct i2c_master_module *const module);
56
57 enum status_code _i2c_master_address_response(
58 struct i2c_master_module *const module);
59
60 enum status_code _i2c_master_send_hs_master_code(
61 struct i2c_master_module *const module,
62 uint8_t hs_master_code);
63
64 #if !defined(__DOXYGEN__)
65
66 /**
67 * \internal Sets configurations to module
68 *
69 * \param[out] module Pointer to software module structure
70 * \param[in] config Configuration structure with configurations to set
71 *
72 * \return Status of setting configuration.
73 * \retval STATUS_OK If module was configured correctly
74 * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
75 * previously set
76 * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible
77 * with set GCLK frequency
78 */
_i2c_master_set_config(struct i2c_master_module * const module,const struct i2c_master_config * const config)79 static enum status_code _i2c_master_set_config(
80 struct i2c_master_module *const module,
81 const struct i2c_master_config *const config)
82 {
83 /* Sanity check arguments. */
84 Assert(module);
85 Assert(module->hw);
86 Assert(config);
87
88 /* Temporary variables. */
89 uint32_t tmp_ctrla;
90 int32_t tmp_baud = 0;
91 int32_t tmp_baud_hs = 0;
92 int32_t tmp_baudlow_hs = 0;
93 enum status_code tmp_status_code = STATUS_OK;
94
95 SercomI2cm *const i2c_module = &(module->hw->I2CM);
96 Sercom *const sercom_hw = module->hw;
97
98 uint8_t sercom_index = _sercom_get_sercom_inst_index(sercom_hw);
99
100 /* Pin configuration */
101 struct system_pinmux_config pin_conf;
102 system_pinmux_get_config_defaults(&pin_conf);
103
104 uint32_t pad0 = config->pinmux_pad0;
105 uint32_t pad1 = config->pinmux_pad1;
106
107 /* SERCOM PAD0 - SDA */
108 if (pad0 == PINMUX_DEFAULT) {
109 pad0 = _sercom_get_default_pad(sercom_hw, 0);
110 }
111 pin_conf.mux_position = pad0 & 0xFFFF;
112 pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
113 system_pinmux_pin_set_config(pad0 >> 16, &pin_conf);
114
115 /* SERCOM PAD1 - SCL */
116 if (pad1 == PINMUX_DEFAULT) {
117 pad1 = _sercom_get_default_pad(sercom_hw, 1);
118 }
119 pin_conf.mux_position = pad1 & 0xFFFF;
120 pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT_WITH_READBACK;
121 system_pinmux_pin_set_config(pad1 >> 16, &pin_conf);
122
123 /* Save timeout on unknown bus state in software module. */
124 module->unknown_bus_state_timeout = config->unknown_bus_state_timeout;
125
126 /* Save timeout on buffer write. */
127 module->buffer_timeout = config->buffer_timeout;
128
129 /* Set whether module should run in standby. */
130 if (config->run_in_standby || system_is_debugger_present()) {
131 tmp_ctrla = SERCOM_I2CM_CTRLA_RUNSTDBY;
132 } else {
133 tmp_ctrla = 0;
134 }
135
136 /* Check and set start data hold timeout. */
137 if (config->start_hold_time != I2C_MASTER_START_HOLD_TIME_DISABLED) {
138 tmp_ctrla |= config->start_hold_time;
139 }
140
141 /* Check and set transfer speed */
142 tmp_ctrla |= config->transfer_speed;
143
144 /* Check and set SCL low timeout. */
145 if (config->scl_low_timeout) {
146 tmp_ctrla |= SERCOM_I2CM_CTRLA_LOWTOUTEN;
147 }
148
149 /* Check and set inactive bus timeout. */
150 if (config->inactive_timeout != I2C_MASTER_INACTIVE_TIMEOUT_DISABLED) {
151 tmp_ctrla |= config->inactive_timeout;
152 }
153
154 /* Check and set SCL clock stretch mode. */
155 if (config->scl_stretch_only_after_ack_bit || (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED)) {
156 tmp_ctrla |= SERCOM_I2CM_CTRLA_SCLSM;
157 }
158
159 /* Check and set slave SCL low extend timeout. */
160 if (config->slave_scl_low_extend_timeout) {
161 tmp_ctrla |= SERCOM_I2CM_CTRLA_SEXTTOEN;
162 }
163
164 /* Check and set master SCL low extend timeout. */
165 if (config->master_scl_low_extend_timeout) {
166 tmp_ctrla |= SERCOM_I2CM_CTRLA_MEXTTOEN;
167 }
168
169 /* Write config to register CTRLA. */
170 i2c_module->CTRLA.reg |= tmp_ctrla;
171
172 /* Set configurations in CTRLB. */
173 i2c_module->CTRLB.reg = SERCOM_I2CM_CTRLB_SMEN;
174
175 /* Find and set baudrate, considering sda/scl rise time */
176 uint32_t fgclk = system_gclk_chan_get_hz(SERCOM0_GCLK_ID_CORE + sercom_index);
177 uint32_t fscl = 1000 * config->baud_rate;
178 uint32_t fscl_hs = 1000 * config->baud_rate_high_speed;
179 uint32_t trise = config->sda_scl_rise_time_ns;
180
181 tmp_baud = (int32_t)(div_ceil(
182 fgclk - fscl * (10 + (fgclk * 0.000000001)* trise), 2 * fscl));
183
184 /* For High speed mode, set the SCL ratio of high:low to 1:2. */
185 if (config->transfer_speed == I2C_MASTER_SPEED_HIGH_SPEED) {
186 tmp_baudlow_hs = (int32_t)((fgclk * 2.0) / (3.0 * fscl_hs) - 1);
187 if (tmp_baudlow_hs) {
188 tmp_baud_hs = (int32_t)(fgclk / fscl_hs) - 2 - tmp_baudlow_hs;
189 } else {
190 tmp_baud_hs = (int32_t)(div_ceil(fgclk, 2 * fscl_hs)) - 1;
191 }
192 }
193
194 /* Check that baudrate is supported at current speed. */
195 if (tmp_baud > 255 || tmp_baud < 0 || tmp_baud_hs > 255 || tmp_baud_hs < 0) {
196 /* Baud rate not supported. */
197 tmp_status_code = STATUS_ERR_BAUDRATE_UNAVAILABLE;
198 }
199 if (tmp_status_code != STATUS_ERR_BAUDRATE_UNAVAILABLE) {
200 /* Baud rate acceptable. */
201 i2c_module->BAUD.reg = SERCOM_I2CM_BAUD_BAUD(tmp_baud) |
202 SERCOM_I2CM_BAUD_HSBAUD(tmp_baud_hs) | SERCOM_I2CM_BAUD_HSBAUDLOW(tmp_baudlow_hs);
203 }
204
205 return tmp_status_code;
206 }
207 #endif /* __DOXYGEN__ */
208
209 /**
210 * \brief Initializes the requested I<SUP>2</SUP>C hardware module
211 *
212 * Initializes the SERCOM I<SUP>2</SUP>C master device requested and sets the provided
213 * software module struct. Run this function before any further use of
214 * the driver.
215 *
216 * \param[out] module Pointer to software module struct
217 * \param[in] hw Pointer to the hardware instance
218 * \param[in] config Pointer to the configuration struct
219 *
220 * \return Status of initialization.
221 * \retval STATUS_OK Module initiated correctly
222 * \retval STATUS_ERR_DENIED If module is enabled
223 * \retval STATUS_BUSY If module is busy resetting
224 * \retval STATUS_ERR_ALREADY_INITIALIZED If setting other GCLK generator than
225 * previously set
226 * \retval STATUS_ERR_BAUDRATE_UNAVAILABLE If given baudrate is not compatible
227 * with set GCLK frequency
228 *
229 */
i2c_master_init(struct i2c_master_module * const module,Sercom * const hw,const struct i2c_master_config * const config)230 enum status_code i2c_master_init(
231 struct i2c_master_module *const module,
232 Sercom *const hw,
233 const struct i2c_master_config *const config)
234 {
235 /* Sanity check arguments. */
236 Assert(module);
237 Assert(hw);
238 Assert(config);
239
240 /* Initialize software module */
241 module->hw = hw;
242
243 SercomI2cm *const i2c_module = &(module->hw->I2CM);
244
245 uint32_t sercom_index = _sercom_get_sercom_inst_index(module->hw);
246 uint32_t pm_index, gclk_index;
247
248 #if (SAML22) || (SAMC20)
249 pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
250 gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
251 #elif (SAML21) || (SAMR30)
252 if (sercom_index == 5) {
253 pm_index = MCLK_APBDMASK_SERCOM5_Pos;
254 gclk_index = SERCOM5_GCLK_ID_CORE;
255 } else {
256 pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
257 gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
258 }
259 #elif (SAMC21)
260 pm_index = sercom_index + MCLK_APBCMASK_SERCOM0_Pos;
261 if (sercom_index == 5) {
262 gclk_index = SERCOM5_GCLK_ID_CORE;
263 } else {
264 gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
265 }
266 #else
267 pm_index = sercom_index + PM_APBCMASK_SERCOM0_Pos;
268 gclk_index = sercom_index + SERCOM0_GCLK_ID_CORE;
269 #endif
270
271 /* Turn on module in PM */
272 #if (SAML21) || (SAMR30)
273 if (sercom_index == 5) {
274 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBD, 1 << pm_index);
275 } else {
276 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
277 }
278 #else
279 system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, 1 << pm_index);
280 #endif
281
282 /* Set up the GCLK for the module */
283 struct system_gclk_chan_config gclk_chan_conf;
284 system_gclk_chan_get_config_defaults(&gclk_chan_conf);
285 gclk_chan_conf.source_generator = config->generator_source;
286 system_gclk_chan_set_config(gclk_index, &gclk_chan_conf);
287 system_gclk_chan_enable(gclk_index);
288 sercom_set_gclk_generator(config->generator_source, false);
289
290 /* Check if module is enabled. */
291 if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_ENABLE) {
292 return STATUS_ERR_DENIED;
293 }
294
295 /* Check if reset is in progress. */
296 if (i2c_module->CTRLA.reg & SERCOM_I2CM_CTRLA_SWRST) {
297 return STATUS_BUSY;
298 }
299
300 #if I2C_MASTER_CALLBACK_MODE == true
301 /* Get sercom instance index and register callback. */
302 uint8_t instance_index = _sercom_get_sercom_inst_index(module->hw);
303 _sercom_set_handler(instance_index, _i2c_master_interrupt_handler);
304 _sercom_instances[instance_index] = module;
305
306 /* Initialize values in module. */
307 module->registered_callback = 0;
308 module->enabled_callback = 0;
309 module->buffer_length = 0;
310 module->buffer_remaining = 0;
311
312 module->status = STATUS_OK;
313 module->buffer = NULL;
314 #endif
315
316 /* Set sercom module to operate in I2C master mode. */
317 i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_MODE(0x5);
318
319 /* Set config and return status. */
320 return _i2c_master_set_config(module, config);
321 }
322
323 /**
324 * \brief Resets the hardware module
325 *
326 * Reset the module to hardware defaults.
327 *
328 * \param[in,out] module Pointer to software module structure
329 */
i2c_master_reset(struct i2c_master_module * const module)330 void i2c_master_reset(struct i2c_master_module *const module)
331 {
332 /* Sanity check arguments */
333 Assert(module);
334 Assert(module->hw);
335
336 SercomI2cm *const i2c_module = &(module->hw->I2CM);
337
338 /* Wait for sync */
339 _i2c_master_wait_for_sync(module);
340
341 /* Disable module */
342 i2c_master_disable(module);
343
344 #if I2C_MASTER_CALLBACK_MODE == true
345 /* Clear all pending interrupts */
346 system_interrupt_enter_critical_section();
347 system_interrupt_clear_pending(_sercom_get_interrupt_vector(module->hw));
348 system_interrupt_leave_critical_section();
349 #endif
350
351 /* Wait for sync */
352 _i2c_master_wait_for_sync(module);
353
354 /* Reset module */
355 i2c_module->CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST;
356 }
357
358 #if !defined(__DOXYGEN__)
359 /**
360 * \internal
361 * Address response. Called when address is answered or timed out.
362 *
363 * \param[in,out] module Pointer to software module structure
364 *
365 * \return Status of address response.
366 * \retval STATUS_OK No error has occurred
367 * \retval STATUS_ERR_DENIED If error on bus
368 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
369 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
370 * acknowledged the address
371 */
_i2c_master_address_response(struct i2c_master_module * const module)372 enum status_code _i2c_master_address_response(
373 struct i2c_master_module *const module)
374 {
375 /* Sanity check arguments */
376 Assert(module);
377 Assert(module->hw);
378
379 SercomI2cm *const i2c_module = &(module->hw->I2CM);
380
381 /* Check for error and ignore bus-error; workaround for BUSSTATE stuck in
382 * BUSY */
383 if (i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) {
384
385 /* Clear write interrupt flag */
386 i2c_module->INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB;
387
388 /* Check arbitration. */
389 if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) {
390 /* Return packet collision. */
391 return STATUS_ERR_PACKET_COLLISION;
392 }
393 /* Check that slave responded with ack. */
394 } else if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
395 /* Slave busy. Issue ack and stop command. */
396 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
397
398 /* Return bad address value. */
399 return STATUS_ERR_BAD_ADDRESS;
400 }
401
402 return STATUS_OK;
403 }
404
405 /**
406 * \internal
407 * Waits for answer on bus.
408 *
409 * \param[in,out] module Pointer to software module structure
410 *
411 * \return Status of bus.
412 * \retval STATUS_OK If given response from slave device
413 * \retval STATUS_ERR_TIMEOUT If no response was given within specified timeout
414 * period
415 */
_i2c_master_wait_for_bus(struct i2c_master_module * const module)416 enum status_code _i2c_master_wait_for_bus(
417 struct i2c_master_module *const module)
418 {
419 /* Sanity check arguments */
420 Assert(module);
421 Assert(module->hw);
422
423 SercomI2cm *const i2c_module = &(module->hw->I2CM);
424
425 /* Wait for reply. */
426 uint16_t timeout_counter = 0;
427 while (!(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) &&
428 !(i2c_module->INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB)) {
429
430 /* Check timeout condition. */
431 if (++timeout_counter >= module->buffer_timeout) {
432 return STATUS_ERR_TIMEOUT;
433 }
434 }
435 return STATUS_OK;
436 }
437 #endif /* __DOXYGEN__ */
438
439 /**
440 * \internal
441 * Send master code for high speed transfer.
442 *
443 * \param[in,out] module Pointer to software module structure
444 * \param[in] hs_master_code 8-bit master code (0000 1XXX)
445 *
446 * \return Status of bus.
447 * \retval STATUS_OK No error happen
448 */
_i2c_master_send_hs_master_code(struct i2c_master_module * const module,uint8_t hs_master_code)449 enum status_code _i2c_master_send_hs_master_code(
450 struct i2c_master_module *const module,
451 uint8_t hs_master_code)
452 {
453 SercomI2cm *const i2c_module = &(module->hw->I2CM);
454 /* Return value. */
455 enum status_code tmp_status;
456
457 /* Set NACK for high speed code */
458 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
459 /* Send high speed code */
460 i2c_module->ADDR.reg = hs_master_code;
461 /* Wait for response on bus. */
462 tmp_status = _i2c_master_wait_for_bus(module);
463 /* Clear write interrupt flag */
464 i2c_module->INTFLAG.reg = SERCOM_I2CM_INTENCLR_MB;
465
466 return tmp_status;
467 }
468
469
470 /**
471 * \internal
472 * Starts blocking read operation.
473 *
474 * \param[in,out] module Pointer to software module struct
475 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
476 *
477 * \return Status of reading packet.
478 * \retval STATUS_OK The packet was read successfully
479 * \retval STATUS_ERR_TIMEOUT If no response was given within
480 * specified timeout period
481 * \retval STATUS_ERR_DENIED If error on bus
482 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
483 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
484 * acknowledged the address
485 *
486 */
_i2c_master_read_packet(struct i2c_master_module * const module,struct i2c_master_packet * const packet)487 static enum status_code _i2c_master_read_packet(
488 struct i2c_master_module *const module,
489 struct i2c_master_packet *const packet)
490 {
491 /* Sanity check arguments */
492 Assert(module);
493 Assert(module->hw);
494 Assert(packet);
495
496 SercomI2cm *const i2c_module = &(module->hw->I2CM);
497
498 /* Return value. */
499 enum status_code tmp_status;
500 uint16_t tmp_data_length = packet->data_length;
501
502 /* Written buffer counter. */
503 uint16_t counter = 0;
504
505 bool sclsm_flag = i2c_module->CTRLA.bit.SCLSM;
506
507 /* Switch to high speed mode */
508 if (packet->high_speed) {
509 _i2c_master_send_hs_master_code(module, packet->hs_master_code);
510 }
511
512 /* Set action to ACK. */
513 i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
514
515 /* Set address and direction bit. Will send start command on bus. */
516 if (packet->ten_bit_address) {
517 /*
518 * Write ADDR.ADDR[10:1] with the 10-bit address. ADDR.TENBITEN must
519 * be set and read/write bit (ADDR.ADDR[0]) equal to 0.
520 */
521 i2c_module->ADDR.reg = (packet->address << 1) |
522 (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
523 SERCOM_I2CM_ADDR_TENBITEN;
524
525 /* Wait for response on bus. */
526 tmp_status = _i2c_master_wait_for_bus(module);
527
528 /* Set action to ack. */
529 i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
530
531 /* Check for address response error unless previous error is
532 * detected. */
533 if (tmp_status == STATUS_OK) {
534 tmp_status = _i2c_master_address_response(module);
535 }
536
537 if (tmp_status == STATUS_OK) {
538 /*
539 * Write ADDR[7:0] register to "11110 address[9:8] 1"
540 * ADDR.TENBITEN must be cleared
541 */
542 i2c_module->ADDR.reg = (((packet->address >> 8) | 0x78) << 1) |
543 (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
544 I2C_TRANSFER_READ;
545 } else {
546 return tmp_status;
547 }
548 } else {
549 i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_READ |
550 (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
551 }
552
553 /* Wait for response on bus. */
554 tmp_status = _i2c_master_wait_for_bus(module);
555
556 /* Set action to ack or nack. */
557 if ((sclsm_flag) && (packet->data_length == 1)) {
558 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
559 } else {
560 i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
561 }
562
563 /* Check for address response error unless previous error is
564 * detected. */
565 if (tmp_status == STATUS_OK) {
566 tmp_status = _i2c_master_address_response(module);
567 }
568
569 /* Check that no error has occurred. */
570 if (tmp_status == STATUS_OK) {
571 /* Read data buffer. */
572 while (tmp_data_length--) {
573 /* Check that bus ownership is not lost. */
574 if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
575 return STATUS_ERR_PACKET_COLLISION;
576 }
577
578 if (module->send_nack && (((!sclsm_flag) && (tmp_data_length == 0)) ||
579 ((sclsm_flag) && (tmp_data_length == 1)))) {
580 /* Set action to NACK */
581 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
582 } else {
583 /* Save data to buffer. */
584 _i2c_master_wait_for_sync(module);
585 packet->data[counter++] = i2c_module->DATA.reg;
586 /* Wait for response. */
587 tmp_status = _i2c_master_wait_for_bus(module);
588 }
589
590 /* Check for error. */
591 if (tmp_status != STATUS_OK) {
592 break;
593 }
594 }
595
596 if (module->send_stop) {
597 /* Send stop command unless arbitration is lost. */
598 _i2c_master_wait_for_sync(module);
599 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
600 }
601
602 /* Save last data to buffer. */
603 _i2c_master_wait_for_sync(module);
604 packet->data[counter] = i2c_module->DATA.reg;
605 }
606
607 return tmp_status;
608 }
609
610 /**
611 * \brief Reads data packet from slave
612 *
613 * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
614 * bus and sends a stop condition when finished.
615 *
616 * \note This will stall the device from any other operation. For
617 * interrupt-driven operation, see \ref i2c_master_read_packet_job.
618 *
619 * \param[in,out] module Pointer to software module struct
620 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
621 *
622 * \return Status of reading packet.
623 * \retval STATUS_OK The packet was read successfully
624 * \retval STATUS_ERR_TIMEOUT If no response was given within
625 * specified timeout period
626 * \retval STATUS_ERR_DENIED If error on bus
627 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
628 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
629 * acknowledged the address
630 */
i2c_master_read_packet_wait(struct i2c_master_module * const module,struct i2c_master_packet * const packet)631 enum status_code i2c_master_read_packet_wait(
632 struct i2c_master_module *const module,
633 struct i2c_master_packet *const packet)
634 {
635 /* Sanity check */
636 Assert(module);
637 Assert(module->hw);
638 Assert(packet);
639
640 #if I2C_MASTER_CALLBACK_MODE == true
641 /* Check if the I2C module is busy with a job. */
642 if (module->buffer_remaining > 0) {
643 return STATUS_BUSY;
644 }
645 #endif
646
647 module->send_stop = true;
648 module->send_nack = true;
649
650 return _i2c_master_read_packet(module, packet);
651 }
652
653 /**
654 * \brief Reads data packet from slave without sending a stop condition when done
655 *
656 * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
657 * bus without sending a stop condition when done, thus retaining ownership of
658 * the bus when done. To end the transaction, a
659 * \ref i2c_master_read_packet_wait "read" or
660 * \ref i2c_master_write_packet_wait "write" with stop condition must be
661 * performed.
662 *
663 * \note This will stall the device from any other operation. For
664 * interrupt-driven operation, see \ref i2c_master_read_packet_job.
665 *
666 * \param[in,out] module Pointer to software module struct
667 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
668 *
669 * \return Status of reading packet.
670 * \retval STATUS_OK The packet was read successfully
671 * \retval STATUS_ERR_TIMEOUT If no response was given within
672 * specified timeout period
673 * \retval STATUS_ERR_DENIED If error on bus
674 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
675 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
676 * acknowledged the address
677 */
i2c_master_read_packet_wait_no_stop(struct i2c_master_module * const module,struct i2c_master_packet * const packet)678 enum status_code i2c_master_read_packet_wait_no_stop(
679 struct i2c_master_module *const module,
680 struct i2c_master_packet *const packet)
681 {
682 /* Sanity check */
683 Assert(module);
684 Assert(module->hw);
685 Assert(packet);
686
687 #if I2C_MASTER_CALLBACK_MODE == true
688 /* Check if the I2C module is busy with a job. */
689 if (module->buffer_remaining > 0) {
690 return STATUS_BUSY;
691 }
692 #endif
693
694 module->send_stop = false;
695 module->send_nack = true;
696
697 return _i2c_master_read_packet(module, packet);
698 }
699
700 /**
701 * \internal
702 * Starts blocking read operation.
703 * \brief Reads data packet from slave without sending a nack signal and a stop
704 * condition when done
705 *
706 * Reads a data packet from the specified slave address on the I<SUP>2</SUP>C
707 * bus without sending a nack signal and a stop condition when done,
708 * thus retaining ownership of the bus when done. To end the transaction, a
709 * \ref i2c_master_read_packet_wait "read" or
710 * \ref i2c_master_write_packet_wait "write" with stop condition must be
711 * performed.
712 *
713 * \note This will stall the device from any other operation. For
714 * interrupt-driven operation, see \ref i2c_master_read_packet_job.
715 *
716 * \param[in,out] module Pointer to software module struct
717 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
718 *
719 * \return Status of reading packet.
720 * \retval STATUS_OK The packet was read successfully
721 * \retval STATUS_ERR_TIMEOUT If no response was given within
722 * specified timeout period
723 * \retval STATUS_ERR_DENIED If error on bus
724 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
725 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
726 * acknowledged the address
727 */
i2c_master_read_packet_wait_no_nack(struct i2c_master_module * const module,struct i2c_master_packet * const packet)728 enum status_code i2c_master_read_packet_wait_no_nack(
729 struct i2c_master_module *const module,
730 struct i2c_master_packet *const packet)
731 {
732 /* Sanity check */
733 Assert(module);
734 Assert(module->hw);
735 Assert(packet);
736
737 #if I2C_MASTER_CALLBACK_MODE == true
738 /* Check if the I2C module is busy with a job. */
739 if (module->buffer_remaining > 0) {
740 return STATUS_BUSY;
741 }
742 #endif
743
744 module->send_stop = false;
745 module->send_nack = false;
746
747 return _i2c_master_read_packet(module, packet);
748 }
749
750 /**
751 * \internal
752 * Starts blocking write operation.
753 *
754 * \param[in,out] module Pointer to software module struct
755 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
756 *
757 * \return Status of write packet.
758 * \retval STATUS_OK The packet was write successfully
759 * \retval STATUS_ERR_TIMEOUT If no response was given within
760 * specified timeout period
761 * \retval STATUS_ERR_DENIED If error on bus
762 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
763 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
764 * acknowledged the address
765 */
_i2c_master_write_packet(struct i2c_master_module * const module,struct i2c_master_packet * const packet)766 static enum status_code _i2c_master_write_packet(
767 struct i2c_master_module *const module,
768 struct i2c_master_packet *const packet)
769 {
770 SercomI2cm *const i2c_module = &(module->hw->I2CM);
771
772 /* Return value. */
773 enum status_code tmp_status;
774 uint16_t tmp_data_length = packet->data_length;
775
776 _i2c_master_wait_for_sync(module);
777
778 /* Switch to high speed mode */
779 if (packet->high_speed) {
780 _i2c_master_send_hs_master_code(module, packet->hs_master_code);
781 }
782
783 /* Set action to ACK. */
784 i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
785
786 /* Set address and direction bit. Will send start command on bus. */
787 if (packet->ten_bit_address) {
788 i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
789 (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos) |
790 SERCOM_I2CM_ADDR_TENBITEN;
791 } else {
792 i2c_module->ADDR.reg = (packet->address << 1) | I2C_TRANSFER_WRITE |
793 (packet->high_speed << SERCOM_I2CM_ADDR_HS_Pos);
794 }
795 /* Wait for response on bus. */
796 tmp_status = _i2c_master_wait_for_bus(module);
797
798 /* Check for address response error unless previous error is
799 * detected. */
800 if (tmp_status == STATUS_OK) {
801 tmp_status = _i2c_master_address_response(module);
802 }
803
804 /* Check that no error has occurred. */
805 if (tmp_status == STATUS_OK) {
806 /* Buffer counter. */
807 uint16_t buffer_counter = 0;
808
809 /* Write data buffer. */
810 while (tmp_data_length--) {
811 /* Check that bus ownership is not lost. */
812 if (!(i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(2))) {
813 return STATUS_ERR_PACKET_COLLISION;
814 }
815
816 /* Write byte to slave. */
817 _i2c_master_wait_for_sync(module);
818 i2c_module->DATA.reg = packet->data[buffer_counter++];
819
820 /* Wait for response. */
821 tmp_status = _i2c_master_wait_for_bus(module);
822
823 /* Check for error. */
824 if (tmp_status != STATUS_OK) {
825 break;
826 }
827
828 /* Check for NACK from slave. */
829 if (i2c_module->STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) {
830 /* Return bad data value. */
831 tmp_status = STATUS_ERR_OVERFLOW;
832 break;
833 }
834 }
835
836 if (module->send_stop) {
837 /* Stop command */
838 _i2c_master_wait_for_sync(module);
839 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
840 }
841 }
842
843 return tmp_status;
844 }
845
846 /**
847 * \brief Writes data packet to slave
848 *
849 * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
850 * and sends a stop condition when finished.
851 *
852 * \note This will stall the device from any other operation. For
853 * interrupt-driven operation, see \ref i2c_master_read_packet_job.
854 *
855 * \param[in,out] module Pointer to software module struct
856 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
857 *
858 * \return Status of write packet.
859 * \retval STATUS_OK If packet was write successfully
860 * \retval STATUS_BUSY If master module is busy with a job
861 * \retval STATUS_ERR_DENIED If error on bus
862 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
863 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
864 * acknowledged the address
865 * \retval STATUS_ERR_TIMEOUT If timeout occurred
866 * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent
867 * data, indicating that slave does not
868 * want more data and was not able to read
869 * last data sent
870 */
i2c_master_write_packet_wait(struct i2c_master_module * const module,struct i2c_master_packet * const packet)871 enum status_code i2c_master_write_packet_wait(
872 struct i2c_master_module *const module,
873 struct i2c_master_packet *const packet)
874 {
875 /* Sanity check */
876 Assert(module);
877 Assert(module->hw);
878 Assert(packet);
879
880 #if I2C_MASTER_CALLBACK_MODE == true
881 /* Check if the I2C module is busy with a job */
882 if (module->buffer_remaining > 0) {
883 return STATUS_BUSY;
884 }
885 #endif
886
887 module->send_stop = true;
888 module->send_nack = true;
889
890 return _i2c_master_write_packet(module, packet);
891 }
892
893 /**
894 * \brief Writes data packet to slave without sending a stop condition when done
895 *
896 * Writes a data packet to the specified slave address on the I<SUP>2</SUP>C bus
897 * without sending a stop condition, thus retaining ownership of the bus when
898 * done. To end the transaction, a \ref i2c_master_read_packet_wait "read" or
899 * \ref i2c_master_write_packet_wait "write" with stop condition or sending a
900 * stop with the \ref i2c_master_send_stop function must be performed.
901 *
902 * \note This will stall the device from any other operation. For
903 * interrupt-driven operation, see \ref i2c_master_read_packet_job.
904 *
905 * \param[in,out] module Pointer to software module struct
906 * \param[in,out] packet Pointer to I<SUP>2</SUP>C packet to transfer
907 *
908 * \return Status of write packet.
909 * \retval STATUS_OK If packet was write successfully
910 * \retval STATUS_BUSY If master module is busy
911 * \retval STATUS_ERR_DENIED If error on bus
912 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
913 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
914 * acknowledged the address
915 * \retval STATUS_ERR_TIMEOUT If timeout occurred
916 * \retval STATUS_ERR_OVERFLOW If slave did not acknowledge last sent
917 * data, indicating that slave do not want
918 * more data
919 */
i2c_master_write_packet_wait_no_stop(struct i2c_master_module * const module,struct i2c_master_packet * const packet)920 enum status_code i2c_master_write_packet_wait_no_stop(
921 struct i2c_master_module *const module,
922 struct i2c_master_packet *const packet)
923 {
924 /* Sanity check */
925 Assert(module);
926 Assert(module->hw);
927 Assert(packet);
928
929 #if I2C_MASTER_CALLBACK_MODE == true
930 /* Check if the I2C module is busy with a job */
931 if (module->buffer_remaining > 0) {
932 return STATUS_BUSY;
933 }
934 #endif
935
936 module->send_stop = false;
937 module->send_nack = true;
938
939 return _i2c_master_write_packet(module, packet);
940 }
941
942 /**
943 * \brief Sends stop condition on bus
944 *
945 * Sends a stop condition on bus.
946 *
947 * \note This function can only be used after the
948 * \ref i2c_master_write_packet_wait_no_stop function. If a stop condition
949 * is to be sent after a read, the \ref i2c_master_read_packet_wait
950 * function must be used.
951 *
952 * \param[in,out] module Pointer to the software instance struct
953 */
i2c_master_send_stop(struct i2c_master_module * const module)954 void i2c_master_send_stop(struct i2c_master_module *const module)
955 {
956 /* Sanity check */
957 Assert(module);
958 Assert(module->hw);
959
960 SercomI2cm *const i2c_module = &(module->hw->I2CM);
961
962 /* Send stop command */
963 _i2c_master_wait_for_sync(module);
964 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(3);
965 }
966
967 /**
968 * \brief Sends nack signal on bus
969 *
970 * Sends a nack signal on bus.
971 *
972 * \note This function can only be used after the
973 * \ref i2c_master_write_packet_wait_no_nack function,
974 * or \ref i2c_master_read_byte function.
975 * \param[in,out] module Pointer to the software instance struct
976 */
i2c_master_send_nack(struct i2c_master_module * const module)977 void i2c_master_send_nack(struct i2c_master_module *const module)
978 {
979 /* Sanity check */
980 Assert(module);
981 Assert(module->hw);
982
983 SercomI2cm *const i2c_module = &(module->hw->I2CM);
984
985 /* Send nack signal */
986 _i2c_master_wait_for_sync(module);
987 i2c_module->CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT;
988 }
989
990 /**
991 * \brief Reads one byte data from slave
992 *
993 * \param[in,out] module Pointer to software module struct
994 * \param[out] byte Read one byte data to slave
995 *
996 * \return Status of reading byte.
997 * \retval STATUS_OK One byte was read successfully
998 * \retval STATUS_ERR_TIMEOUT If no response was given within
999 * specified timeout period
1000 * \retval STATUS_ERR_DENIED If error on bus
1001 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
1002 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
1003 * acknowledged the address
1004 */
i2c_master_read_byte(struct i2c_master_module * const module,uint8_t * byte)1005 enum status_code i2c_master_read_byte(
1006 struct i2c_master_module *const module,
1007 uint8_t *byte)
1008 {
1009 enum status_code tmp_status;
1010 SercomI2cm *const i2c_module = &(module->hw->I2CM);
1011
1012 i2c_module->CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT;
1013 /* Write byte to slave. */
1014 _i2c_master_wait_for_sync(module);
1015 *byte = i2c_module->DATA.reg;
1016 /* Wait for response. */
1017 tmp_status = _i2c_master_wait_for_bus(module);
1018
1019 return tmp_status;
1020 }
1021
1022 /**
1023 * \brief Write one byte data to slave
1024 *
1025 * \param[in,out] module Pointer to software module struct
1026 * \param[in] byte Send one byte data to slave
1027 *
1028 * \return Status of writing byte.
1029 * \retval STATUS_OK One byte was write successfully
1030 * \retval STATUS_ERR_TIMEOUT If no response was given within
1031 * specified timeout period
1032 * \retval STATUS_ERR_DENIED If error on bus
1033 * \retval STATUS_ERR_PACKET_COLLISION If arbitration is lost
1034 * \retval STATUS_ERR_BAD_ADDRESS If slave is busy, or no slave
1035 * acknowledged the address
1036 */
i2c_master_write_byte(struct i2c_master_module * const module,uint8_t byte)1037 enum status_code i2c_master_write_byte(
1038 struct i2c_master_module *const module,
1039 uint8_t byte)
1040 {
1041 enum status_code tmp_status;
1042 SercomI2cm *const i2c_module = &(module->hw->I2CM);
1043
1044 /* Write byte to slave. */
1045 _i2c_master_wait_for_sync(module);
1046 i2c_module->DATA.reg = byte;
1047 /* Wait for response. */
1048 tmp_status = _i2c_master_wait_for_bus(module);
1049 return tmp_status;
1050 }
1051