1 /*
2  * @ : Copyright (c) 2021 Phytium Information Technology, Inc.
3  *
4  * SPDX-License-Identifier: Apache-2.0.
5  *
6  * @Date: 2021-04-02 18:32:54
7  * @LastEditTime: 2021-05-24 14:33:45
8  * @Description:  Description of file
9  *
10  * @Modify History:
11  * * * Ver   Who        Date         Changes
12  * * ----- ------     --------    --------------------------------------
13  */
14 
15 #ifndef QSPI_HW_H
16 #define QSPI_HW_H
17 
18 #ifdef __cplusplus
19 extern "C"
20 {
21 #endif
22 
23 #include "ft_qspi.h"
24 #include "ft_types.h"
25 
26 /* register definition */
27 #define FT_REG_QSPI_CAP_OFFSET (0x00)       /* Flash capacity setting register */
28 #define FT_REG_QSPI_RD_CFG_OFFSET (0x04)    /* Address access reads configuration registers */
29 #define FT_REG_QSPI_WR_CFG_OFFSET (0x08)    /* Write buffer flush register */
30 #define FT_REG_QSPI_FLUSH_OFFSET (0x0C)     /* Write buffer flush register */
31 #define FT_REG_QSPI_CMD_PORT_OFFSET (0x10)  /* Command port register */
32 #define FT_REG_QSPI_ADDR_PORT_OFFSET (0x14) /* Address port register */
33 #define FT_REG_QSPI_HD_PORT_OFFSET (0x18)   /* Upper bit port register */
34 #define FT_REG_QSPI_LD_PORT_OFFSET (0x1C)   /* low bit port register */
35 #define FT_REG_QSPI_FUN_SET_OFFSET (0x20)   /* CS setting register  */
36 #define FT_REG_QSPI_WIP_RD_OFFSET (0x24)    /* WIP reads the Settings register */
37 #define FT_REG_QSPI_WP_OFFSET (0x28)        /* WP register */
38 #define FT_REG_QSPI_MODE_OFFSET (0x2C)      /* Mode setting register */
39 
40 /*QSPI_CAP*/
41 #define FT_REG_QSPI_CAP_FLASH_NUM(data) ((data) << 3) /* Flash number */
42 #define FT_REG_QSPI_CAP_FLASH_CAP(data) ((data) << 0) /*  The flash capacity */
43 
44 /* RD_CFG */
45 #define FT_RD_CFG_CMD(data) ((data) << 24)       /* Read Command */
46 #define FT_RD_CFG_THROUGH(data) ((data) << 23)   /*  The programming flag in the status register */
47 #define FT_RD_CFG_TRANSFER(data) ((data) << 20)  /*  */
48 #define FT_RD_CFG_ADDR_SEL(data) ((data) << 19)  /*  */
49 #define FT_RD_CFG_LATENCY(data) ((data) << 18)   /*  */
50 #define FT_RD_CFG_MODE_BYTE(data) ((data) << 17) /*  */
51 #define FT_RD_CFG_CMD_SIGN(data) ((data) << 9)   /*  */
52 #define FT_RD_CFG_DUMMY(data) ((data) << 4)      /*  */
53 #define FT_RD_CFG_D_BUFFER(data) ((data) << 3)   /*  */
54 #define FT_RD_CFG_SCK_SEL(data) ((data) << 0)    /*  */
55 
56 /*QSPI_WR_CFG*/
57 #define FT_WR_CFG_CMD(data) ((data) << 24)
58 #define FT_WR_CFG_WAIT(data) ((data) << 9)
59 #define FT_WR_CFG_THROUGH(data) ((data) << 8)
60 #define FT_WR_CFG_TRANSFER(data) ((data) << 5)
61 #define FT_WR_CFG_ADDRSEL(data) ((data) << 4)
62 #define FT_WR_CFG_MODE(data) ((data) << 3)
63 #define FT_WR_CFG_SCK_SEL(data) ((data) << 0)
64 
65 /*QSPI_CMD_PORT*/
66 #define FT_CMD_PORT_CMD(data) ((data) << 24)
67 #define FT_CMD_PORT_WAIT(data) ((data) << 22)
68 #define FT_CMD_PORT_THROUGH(data) ((data) << 21)
69 #define FT_CMD_PORT_CS(data) ((data) << 19)
70 #define FT_CMD_PORT_TRANSFER(data) ((data) << 16)
71 #define FT_CMD_PORT_ADDR(data) ((data) << 15)
72 #define FT_CMD_PORT_LATENCY(data) ((data) << 14)
73 #define FT_CMD_PORT_DATA_TRANS(data) ((data) << 13)
74 #define FT_CMD_PORT_ADDR_SEL(data) ((data) << 12)
75 #define FT_CMD_PORT_DUMMY(data) ((data) << 7)
76 #define FT_CMD_PORT_P_BUFFER(data) ((data) << 6)
77 #define FT_CMD_PORT_RW_NUM(data) ((data) << 3)
78 #define FT_CMD_PORT_CLK_SEL(data) ((data) << 0)
79 
80 /*QSPI_FUN_SET*/
81 #define FT_FUN_SET_CS_HOLD(data) ((data) << 24)
82 #define FT_FUN_SET_CS_SETUP(data) ((data) << 16)
83 #define FT_FUN_SET_CS_DELAY(data) ((data) << 0)
84 
85 /*QSPI_WIP_RD*/
86 #define FT_WIP_RD_CMD(data) ((data) << 24)
87 #define FT_WIP_RD_TRANSFER(data) ((data) << 3)
88 #define FT_WIP_RD_SCK_SEL(data) ((data) << 0)
89 
90 /*QSPI_WP*/
91 #define FT_WP_EN(data) ((data) << 17)
92 #define FT_WP_WP(data) ((data) << 16)
93 #define FT_WP_HOLD(data) ((data) << 8)
94 #define FT_WP_SETUP(data) ((data) << 0)
95 
96 /*QSPI_MODE*/
97 #define FT_MODE_VALID(data) ((data) << 8)
98 #define FT_MODE_MODE(data) ((data) << 0)
99 
100 #define FT_QSPI_FLASH_CAP_4MB 0
101 #define FT_QSPI_FLASH_CAP_8MB 1
102 #define FT_QSPI_FLASH_CAP_16MB 2
103 #define FT_QSPI_FLASH_CAP_32MB 3
104 #define FT_QSPI_FLASH_CAP_64MB 4
105 #define FT_QSPI_FLASH_CAP_128MB 5
106 #define FT_QSPI_FLASH_CAP_256MB 6
107 
108 #define FT_QSPI_ADDR_SEL_3 0
109 #define FT_QSPI_ADDR_SEL_4 1
110 
111 #define FT_QSPI_SCK_DIV_128 0
112 #define FT_QSPI_SCK_DIV_2 1
113 #define FT_QSPI_SCK_DIV_4 2
114 #define FT_QSPI_SCK_DIV_8 3
115 #define FT_QSPI_SCK_DIV_16 4
116 #define FT_QSPI_SCK_DIV_32 5
117 #define FT_QSPI_SCK_DIV_64 6
118 
119 #define FT_QSPI_TRANSFER_1_1_1 0
120 #define FT_QSPI_TRANSFER_1_1_2 1
121 #define FT_QSPI_TRANSFER_1_1_4 2
122 #define FT_QSPI_TRANSFER_1_2_2 3
123 #define FT_QSPI_TRANSFER_1_4_4 4
124 #define FT_QSPI_TRANSFER_2_2_2 5
125 #define FT_QSPI_TRANSFER_4_4_4 6
126 
127     /* typedefs */
128     /*QSPI_RD_CFG*/
129     typedef union
130     {
131         u32 data;
132         struct
133         {
134             u32 rdSckSel : 3;   /* 2:0   */
135             u32 dBuffer : 1;    /* 3     */
136             u32 dummy : 5;      /* 8:4   */
137             u32 cmdSign : 8;    /* 16:9  */
138             u32 modeByte : 1;   /* 17    */
139             u32 rdLatency : 1;  /* 18    */
140             u32 rdAddrSel : 1;  /* 19    */
141             u32 rdTransfer : 3; /* 22:20 */
142             u32 rdThrough : 1;  /* 23    */
143             u32 rdCmd : 8;      /* 31:24 */
144         } val;
145     } FQSpi_RdCfgReg_t;
146 
147     /*QSPI_WR_CFG*/
148     typedef union
149     {
150         u32 data;
151         struct
152         {
153             u32 wrSckSel : 3;   /* 2:0   */
154             u32 wrMode : 1;     /* 3     */
155             u32 wrAddrsel : 1;  /* 4     */
156             u32 wrTransfer : 3; /* 7:5   */
157             u32 wrThrough : 1;  /* 8     */
158             u32 wrWait : 1;     /* 9     */
159             u32 wrRes : 14;     /* 23:10 */
160             u32 wrCmd : 8;      /* 31:24 */
161         } val;
162     } FQSpi_WrCfgReg_t;
163 
164     /*QSPI_CMD_PORT*/
165     typedef union
166     {
167         u32 data;
168         struct
169         {
170             u32 sckSel : 3;       /* 2:0   */
171             u32 rwMum : 3;        /* 5:3   */
172             u32 pBuffer : 1;      /* 6     */
173             u32 dummy : 5;        /* 11:7  */
174             u32 addrSel : 1;      /* 12    */
175             u32 dataTransfer : 1; /* 13    */
176             u32 latency : 1;      /* 14    */
177             u32 cmdAddr : 1;      /* 15    */
178             u32 transfer : 3;     /* 18:16 */
179             u32 cs : 2;           /* 20:19 */
180             u32 through : 1;      /* 21    */
181             u32 wait : 1;         /* 22    */
182             u32 res : 1;          /* 23    */
183             u32 cmd : 8;          /* 31:24 */
184         } val;
185     } FQSpi_CmdPortReg_t;
186 
187     /**
188  * @name: FQSpi_Reset
189  * @msg:  This routine performs the QSPI controller initialization.
190  * @in param: pQspi
191  * @return {*}
192  */
193     void FQSpi_Reset(FQSpi_t *pQspi);
194 
195 #ifdef __cplusplus
196 }
197 #endif
198 
199 #endif // !
200