1 /** 2 ********************************************************************************* 3 * 4 * @file ald_nand.h 5 * @brief Header file of EBI_NAND module driver 6 * 7 * @version V1.0 8 * @date 07 Dec 2019 9 * @author AE Team 10 * @note 11 * Change Logs: 12 * Date Author Notes 13 * 07 Dec 2019 AE Team The first version 14 * 15 * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved. 16 * 17 * SPDX-License-Identifier: Apache-2.0 18 * 19 * Licensed under the Apache License, Version 2.0 (the License); you may 20 * not use this file except in compliance with the License. 21 * You may obtain a copy of the License at 22 * 23 * www.apache.org/licenses/LICENSE-2.0 24 * 25 * Unless required by applicable law or agreed to in writing, software 26 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 27 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 * See the License for the specific language governing permissions and 29 * limitations under the License. 30 ********************************************************************************** 31 */ 32 33 #ifndef __ALD_NAND_H_ 34 #define __ALD_NAND_H_ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #include "ald_ebi.h" 41 42 /** @addtogroup ES32FXXX_ALD 43 * @{ 44 */ 45 46 /** @addtogroup NAND 47 * @{ 48 */ 49 50 /** @defgroup NAND_Public_Types NAND Public Types 51 * @{ 52 */ 53 54 /** 55 * @brief NAND State structures definition 56 */ 57 typedef enum { 58 ALD_NAND_STATE_RESET = 0x00U, /**< NAND not yet initialized or disabled */ 59 ALD_NAND_STATE_READY = 0x01U, /**< NAND initialized and ready for use */ 60 ALD_NAND_STATE_BUSY = 0x02U, /**< NAND internal process is ongoing */ 61 ALD_NAND_STATE_ERROR = 0x03U /**< NAND error state */ 62 } ald_nand_state_t; 63 64 /** 65 * @brief NAND Memory electronic signature Structure definition 66 */ 67 typedef struct { 68 uint8_t maker_id; /**< Maker id */ 69 uint8_t device_id; /**< Device id */ 70 uint8_t third_id; /**< Third id */ 71 uint8_t fourth_id; /**< Fourth id */ 72 } nand_id_t; 73 74 /** 75 * @brief NAND Memory address Structure definition 76 */ 77 typedef struct 78 { 79 uint16_t page; /**< NAND memory Page address */ 80 uint16_t plane; /**< NAND memory Plane address */ 81 uint16_t block; /**< NAND memory Block address */ 82 } nand_address_t; 83 84 /** 85 * @brief NAND Memory info Structure definition 86 */ 87 typedef struct 88 { 89 uint32_t page_size; /**< NAND memory page (without spare area) size measured in bytes */ 90 uint32_t spare_size; /**< NAND memory spare area size measured in bytes */ 91 uint32_t block_size; /**< NAND memory block size measured in number of pages */ 92 uint32_t block_nbr; /**< NAND memory number of total block */ 93 uint32_t plane_nbr; /**< NAND memory number of planes */ 94 uint32_t plane_size; /**< NAND memory plane size measured in number of blocks */ 95 type_func_t extra_cmd; /**< NAND extra command needed for Page reading mode */ 96 } nand_device_cfg_t; 97 98 /** 99 * @brief NAND handle Structure definition 100 */ 101 typedef struct 102 { 103 EBI_NAND_TypeDef *instance; /**< Register base address */ 104 ald_ebi_nand_init_t init; /**< NAND device control configuration parameters */ 105 lock_state_t lock; /**< NAND locking object */ 106 __IO ald_nand_state_t state; /**< NAND device access state */ 107 nand_device_cfg_t config; /**< NAND phusical characteristic information structure */ 108 } nand_handle_t; 109 110 /** 111 * @} 112 */ 113 114 /** 115 * @defgroup Nand_Private_Constants Nand Private Constants 116 * @{ 117 */ 118 119 #define NAND_DEVICE1 EBI_BANK2 120 #define NAND_DEVICE2 EBI_BANK3 121 #define NAND_WRITE_TIMEOUT 1000U 122 #define CMD_AREA (1U<<16U) /* A16 = CLE high */ 123 #define ADDR_AREA (1U<<17U) /* A17 = ALE high */ 124 #define NAND_CMD_AREA_A ((uint8_t)0x00U) 125 #define NAND_CMD_AREA_B ((uint8_t)0x01U) 126 #define NAND_CMD_AREA_C ((uint8_t)0x50U) 127 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) 128 #define NAND_CMD_WRITE0 ((uint8_t)0x80U) 129 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) 130 #define NAND_CMD_ERASE0 ((uint8_t)0x60U) 131 #define NAND_CMD_ERASE1 ((uint8_t)0xD0U) 132 #define NAND_CMD_READID ((uint8_t)0x90U) 133 #define NAND_CMD_STATUS ((uint8_t)0x70U) 134 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) 135 #define NAND_CMD_RESET ((uint8_t)0xFFU) 136 /* NAND memory status */ 137 #define NAND_VALID_ADDRESS 0x00000100U 138 #define NAND_INVALID_ADDRESS 0x00000200U 139 #define NAND_TIMEOUT_ERROR 0x00000400U 140 #define NAND_BUSY 0x00000000U 141 #define NAND_ERROR 0x00000001U 142 #define NAND_READY 0x00000040U 143 /** 144 * @} 145 */ 146 147 /** @defgroup Nand_Private_Macros Nand Private Macros 148 * @{ 149 */ 150 #define ARRAY_ADDRESS(x , y) ((x)->page + \ 151 (((x)->block + (((x)->plane) * \ 152 ((y)->config.plane_size))) * ((y)->config.block_size))) 153 #define COLUMN_ADDRESS( x) ((x)->config.page_size) 154 #define ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */ 155 #define ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */ 156 #define ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */ 157 #define ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */ 158 #define COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */ 159 #define COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */ 160 /** 161 * @} 162 */ 163 164 /** @addtogroup Nand_Public_Functions 165 * @{ 166 */ 167 /** @addtogroup Nand_Public_Functions_Group1 168 * @{ 169 */ 170 /* Initialization/de-initialization functions */ 171 ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming); 172 ald_status_t ald_nand_deinit(nand_handle_t *hperh); 173 ald_status_t ald_nand_reset(nand_handle_t *hperh); 174 void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg); 175 /** 176 * @} 177 */ 178 /** @addtogroup Nand_Public_Functions_Group2 179 * @{ 180 */ 181 /* IO operation functions */ 182 ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id); 183 ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); 184 ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); 185 ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); 186 ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr); 187 ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); 188 ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); 189 ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); 190 ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr); 191 ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr); 192 /** 193 * @} 194 */ 195 /** @addtogroup Nand_Public_Functions_Group3 196 * @{ 197 */ 198 /* NAND Control functions */ 199 void ald_nand_irq_handler(nand_handle_t *hperh); 200 void ald_nand_irq_cbk(nand_handle_t *hperh); 201 uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr); 202 uint32_t ald_nand_read_status(nand_handle_t *hperh); 203 ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh); 204 ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh); 205 ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh); 206 ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout); 207 /** 208 * @} 209 */ 210 /** 211 * @} 212 */ 213 /** 214 * @} 215 */ 216 /** 217 * @} 218 */ 219 #ifdef __cplusplus 220 } 221 #endif 222 #endif 223