1 /*
2 * Copyright (C) 2016 YunOS Project. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <stdint.h>
18 #include <string.h>
19 #include <assert.h>
20 #include <stdio.h>
21 #include <unistd.h>
22 #include <fcntl.h>
23 #include <sys/types.h>
24 #include <sys/stat.h>
25 #include <syslog.h>
26 #ifndef CONFIG_KERNEL_NONE
27 #include <csi_kernel.h>
28 #endif
29 #include "ethernet_enc28j60.h"
30
31 #include "pin.h"
32 #include "soc.h"
33 #include "drv_spi.h"
34 #include "drv_gpio.h"
35 #include "drv_eth.h"
36 #include "drv_eth_phy.h"
37 #include "drv_eth_mac.h"
38
39 #include <errno.h>
40
41 #define NET_HWADDR_LEN 6
42 #define THIS_MODULE MODULE_DEV_ETH
43 #define MAX_SPI_TRANSFER_LEN 512
44 #define MAX_RECV_ERROR_CNT 50
45
46 static uint8_t Enc28j60Bank;
47 static uint16_t NextPacketPtr;
48 gpio_pin_handle_t pin_int = NULL;
49
50 typedef int (*gpio_interrupt_t)(int irqno);
51
52 static spi_handle_t g_net_spi_hd = NULL;
53 static gpio_pin_handle_t pgpio_pin_handle1;
54 //static k_sem_handle_t g_sem_spi_tx_hd = NULL;
55 //static k_sem_handle_t g_sem_spi_rx_hd = NULL;
56
57 static eth_mac_priv_t s_eth_instance[CONFIG_ETH_NUM];
58 static eth_phy_priv_t s_phy_instance[CONFIG_ETH_NUM];
59
60 static uint8_t g_hw_addr[NET_HWADDR_LEN] = {0};
61
62 static uint8_t enc28j60ReadOp(uint8_t op, uint8_t address);
63 static void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data);
64 static void enc28j60ReadBuffer(const uint16_t len, uint8_t *data);
65 static void enc28j60WriteBuffer(uint16_t len, uint8_t *data);
66 static void enc28j60SetBank(uint8_t address);
67 static uint8_t enc28j60Read(uint8_t address);
68 static void enc28j60Write(uint8_t address, uint8_t data);
69 static uint32_t enc28j60PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data);
70 static uint32_t enc28j60Phyregread(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data);
71 static void enc28j60Init(const uint8_t *macaddr);
72 static int enc28j60Reset(int obj);
73 static uint16_t enc28j60GetRxFreeSpace(void);
74 static void enc28j60_int_handle(uint32_t event);
75 static int enc28j60_set_interrupt(pin_t gpio_pin);
76 extern void mdelay(uint32_t ms);
77
78 /**
79 * interrupt handle function to post sem for handle
80 *
81 * @param irqno the irq number of network
82 *
83 */
enc28j60_int_handle(uint32_t event)84 static void enc28j60_int_handle(uint32_t event)
85 {
86 eth_mac_priv_t *eth_priv = &s_eth_instance[0];
87 uint8_t int_stat, ptkcnt, estat;
88 uint16_t freespace;
89 uint16_t status_vec_ptr;
90 uint8_t status_vec[7];
91 bool reset = 0;
92
93 csi_gpio_pin_irq_set(pin_int, GPIO_IRQ_MODE_LOW_LEVEL, 0);
94 //enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIE, EIE_INTIE);
95
96 int_stat = enc28j60Read(EIR); /* read EIR register data */;
97
98 // error flags to be handled first
99 if (int_stat & EIR_RXERIF) {
100 ptkcnt = enc28j60Read(EPKTCNT);
101 freespace = enc28j60GetRxFreeSpace();
102 #ifndef CONFIG_TEST_TTCP
103
104 if ((ptkcnt == 0xFF) || (freespace < MAX_FRAMELEN)) {
105 /* do nothing, data in buffer will be read out */
106 printf("Rx buffer has %d packets and %d bytes free space\n", ptkcnt, freespace);
107 } else {
108 printf("something is wrong other than no buffer.\n");
109 }
110
111 #endif
112 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_RXERIF);
113
114 if (ptkcnt > MAX_RECV_ERROR_CNT) {
115 reset = 1;
116 }
117 }
118
119 if (int_stat & EIR_TXERIF) {
120 estat = enc28j60Read(ESTAT);
121
122 if ((estat & ESTAT_TXABRT) || (estat & ESTAT_LATECOL)) {
123 printf("ESTAT=0x%x\n", estat);
124 status_vec_ptr = enc28j60Read(ETXNDL);
125 status_vec_ptr |= enc28j60Read(ETXNDH) << 8;
126 status_vec_ptr++;
127 enc28j60Write(ERDPTL, status_vec_ptr);
128 enc28j60Write(ERDPTH, status_vec_ptr >> 8);
129 enc28j60ReadBuffer(7, status_vec);
130 printf("status vector:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n",
131 status_vec[0], status_vec[1], status_vec[2], status_vec[3], status_vec[4], status_vec[5], status_vec[6]);
132 reset = 1;
133 }
134
135 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF);
136 }
137
138 if (reset) {
139 if (enc28j60Reset(RST_ENC28J60_ALL) == 0) {
140 printf("reset OK \n");
141 /* init enc28j60 module */
142 uint8_t macaddr[6];
143
144 csi_eth_mac_get_macaddr(NULL, (eth_mac_addr_t *)macaddr);
145
146 enc28j60Init(macaddr);
147
148 printf("enc28j60 init OK \n");
149 enc28j60_set_interrupt(PA5_A8);
150 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE);
151 return;
152 }
153 }
154
155 if (int_stat & EIR_PKTIF) {
156 ptkcnt = enc28j60Read(EPKTCNT); //just for debugging
157
158 //EIR_PKTIF will be cleared if all data is read out
159 eth_priv->cb_event((eth_mac_handle_t)eth_priv, CSI_ETH_MAC_EVENT_RX_FRAME);
160 }
161
162 if (int_stat & EIR_TXIF) {
163 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF);
164 //eth_priv->cb_event((eth_mac_handle_t)eth_priv, CSI_ETH_MAC_EVENT_TX_FRAME);
165 }
166
167 if (int_stat & EIR_LINKIF) {
168 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, EIR_LINKIF);
169 eth_priv->cb_event((eth_mac_handle_t)eth_priv, CSI_ETH_MAC_EVENT_LINK_CHANGE);
170 }
171
172 //clear all interrupt falgs. In fact, EIR_PKTIF can not be cleared
173 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIR, 0xFF & (~(EIR_PKTIF | EIR_LINKIF)));
174
175 // don't enable interrupt if events not handled
176 if (!(int_stat & (EIR_PKTIF | EIR_LINKIF))) {
177 //enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE);
178 csi_gpio_pin_irq_set(pin_int, GPIO_IRQ_MODE_LOW_LEVEL, 1);
179 }
180
181 }
182
enc28j60_spi_transfer_callback(spi_event_e event)183 void enc28j60_spi_transfer_callback(spi_event_e event)
184 {
185 if (event == SPI_EVENT_TRANSFER_COMPLETE) {
186
187 } else if (event == SPI_EVENT_TX_COMPLETE) {
188 //csi_kernel_sem_post(g_sem_spi_tx_hd);
189 } else if (event == SPI_EVENT_RX_COMPLETE) {
190 //csi_kernel_sem_post(g_sem_spi_rx_hd);
191 } else if (event == SPI_EVENT_DATA_LOST) {
192 printf("TRANSFER_DATA_LOST\n");
193 } else {
194 printf("TRANSFER_MODE_FAULT\n");
195 }
196 }
197
enc28j60_spi_cs_status_change(int status)198 void enc28j60_spi_cs_status_change(int status)
199 {
200 csi_gpio_pin_write(pgpio_pin_handle1, status);
201 }
202
enc28j60_spi_send(spi_handle_t handle,const void * data,uint32_t num)203 static int32_t enc28j60_spi_send(spi_handle_t handle, const void *data, uint32_t num)
204 {
205 csi_spi_send(handle, data, num, 1);
206 // csi_kernel_sem_wait(g_sem_spi_tx_hd, -1);
207
208 return 0;
209 }
210
enc28j60_spi_receive(spi_handle_t handle,void * data,uint32_t num)211 static int32_t enc28j60_spi_receive(spi_handle_t handle, void *data, uint32_t num)
212 {
213 csi_spi_receive(handle, data, num, 1);
214 //csi_kernel_sem_wait(g_sem_spi_rx_hd, -1);
215
216 return 0;
217 }
218
219 /**
220 * read ctrl register
221 * @param op operation cmd
222 * @param register address
223 *
224 * @return
225 * -register data
226 */
enc28j60ReadOp(uint8_t op,uint8_t address)227 static uint8_t enc28j60ReadOp(uint8_t op, uint8_t address)
228 {
229 uint8_t dat = 0;
230
231 ENC28J60_CSL();
232
233 dat = (op | (address & ADDR_MASK));
234
235 uint8_t rdata[1] = {0};
236
237 enc28j60_spi_send(g_net_spi_hd, &dat, 1);
238
239 enc28j60_spi_receive(g_net_spi_hd, &rdata[0], 1);
240
241 /* do dummy read if needed (for mac and mii, see datasheet page 29) */
242 if (address & 0x80) {
243 enc28j60_spi_receive(g_net_spi_hd, &rdata[0], 1);
244 }
245
246 /* release CS */
247 ENC28J60_CSH();
248 return rdata[0];
249
250 }
251
252 /**
253 * write ctrl cmd to register
254 * @param op operation cmd
255 * @param register address
256 * @param data the data to be set
257 *
258 * @return
259 * -NULL
260 */
enc28j60WriteOp(uint8_t op,uint8_t address,uint8_t data)261 static void enc28j60WriteOp(uint8_t op, uint8_t address, uint8_t data)
262 {
263 char dat = 0;
264
265 ENC28J60_CSL();
266 /* issue write command */
267 dat = op | (address & ADDR_MASK);
268
269 enc28j60_spi_send(g_net_spi_hd, &dat, 1);
270
271 dat = data;
272 enc28j60_spi_send(g_net_spi_hd, &dat, 1);
273
274 ENC28J60_CSH();
275 }
276
277 /**
278 * read buffer data
279 * @param len the data length waint to read
280 * @param data the data buffer
281 *
282 * @return
283 * -NULL
284 */
enc28j60ReadBuffer(uint16_t len,uint8_t * data)285 static void enc28j60ReadBuffer(uint16_t len, uint8_t *data)
286 {
287 char ops_ctr = ENC28J60_READ_BUF_MEM;
288
289 ENC28J60_CSL();
290 /* issue read command */
291
292 enc28j60_spi_send(g_net_spi_hd, &ops_ctr, 1);
293
294 enc28j60_spi_receive(g_net_spi_hd, (char *)&data[0], len);
295
296 ENC28J60_CSH();
297 }
298
299 /**
300 * write data to buffer
301 * @param len the data length waint to write
302 * @param data the data buffer pointer
303 *
304 * @return
305 * -NULL
306 */
enc28j60WriteBuffer(uint16_t len,uint8_t * data)307 static void enc28j60WriteBuffer(uint16_t len, uint8_t *data)
308 {
309 char ops_ctr = ENC28J60_WRITE_BUF_MEM;
310
311 ENC28J60_CSL();
312 /* issue write command */
313 //drv_porting_spi_write(NULL, &ops_ctr, 1);
314
315 enc28j60_spi_send(g_net_spi_hd, &ops_ctr, 1);
316
317 enc28j60_spi_send(g_net_spi_hd, &data[0], len);
318
319 ENC28J60_CSH();
320 }
321
322 /**
323 * select the bank to operation
324 * @param address the bank address
325 *
326 * @return
327 * -NULL
328 */
enc28j60SetBank(uint8_t address)329 static void enc28j60SetBank(uint8_t address)
330 {
331 /* set the bank (if needed) */
332 if ((address & BANK_MASK) != Enc28j60Bank) {
333 /* set the bank */
334 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1 | ECON1_BSEL0));
335 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK) >> 5);
336 Enc28j60Bank = (address & BANK_MASK);
337 }
338 }
339
340 /**
341 * read ctrl register data
342 * @param address the ctrl register address
343 *
344 * @return
345 * -ctrl register data
346 */
enc28j60Read(uint8_t address)347 static uint8_t enc28j60Read(uint8_t address)
348 {
349 /* set the bank */
350 enc28j60SetBank(address);
351 /* do the read */
352 return enc28j60ReadOp(ENC28J60_READ_CTRL_REG, address);
353 }
354
355 /**
356 * write data to ctrl register
357 * @param address the ctrl register address
358 * @param data ctrl register cmd
359 *
360 * @return
361 * - NULL
362 */
enc28j60Write(uint8_t address,uint8_t data)363 static void enc28j60Write(uint8_t address, uint8_t data)
364 {
365 /* set the bank */
366 enc28j60SetBank(address);
367 /* do the write */
368 enc28j60WriteOp(ENC28J60_WRITE_CTRL_REG, address, data);
369 }
370
371 /**
372 * write data to phy register
373 * @param address the phy register address
374 * @param data phy register cmd
375 *
376 * @return
377 * - NULL
378 */
enc28j60PhyWrite(uint8_t phy_addr,uint8_t reg_addr,uint16_t data)379 static uint32_t enc28j60PhyWrite(uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
380 {
381 int retry = 0;
382
383 /* set the PHY register address */
384 enc28j60Write(MIREGADR, phy_addr);
385 /* write the PHY data */
386 enc28j60Write(MIWRL, data);
387 enc28j60Write(MIWRH, data >> 8);
388
389 /* wait until the PHY write completes */
390 while (enc28j60Read(MISTAT) & MISTAT_BUSY) {
391 retry++;
392
393 if (retry > 0xFFF) {
394 printf("write Phyreg_status error \n");
395 return -1;
396 }
397 }
398
399 return 0;
400 }
401
402 /**
403 * read data from phy register
404 * @param address the phy register address
405 *
406 * @return
407 * -the data of phy register
408 */
enc28j60Phyregread(uint8_t phy_addr,uint8_t reg_addr,uint16_t * data)409 static uint32_t enc28j60Phyregread(uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
410 {
411 uint8_t temp;
412 int retry = 0;
413
414 temp = enc28j60Read(MICMD);
415 /* set the PHY register address */
416 enc28j60Write(MIREGADR, phy_addr);
417
418 enc28j60Write(MICMD, temp | MICMD_MIIRD);
419
420 /* Loop to wait until the PHY register has been read through the MII */
421 while ((enc28j60Read(MISTAT) & MISTAT_BUSY)) {
422 if (retry++ > 0xFFF) {
423 printf("read Phyreg_status error \n");
424 return -1;
425 }
426 }
427
428 enc28j60Write(MICMD, temp & (~MICMD_MIIRD)); /* clear bit MICMD.MIIRD */
429
430 /* Obtain results and return */
431 *data = enc28j60Read(MIRDL);
432 *data |= (enc28j60Read(MIRDH) << 8);
433
434 return *data;
435 }
436
437 /**
438 * init ethernet ctrl register
439 * @param address the MAC address
440 *
441 * @return
442 * - NULL
443 */
enc28j60Init(const uint8_t * macaddr)444 static void enc28j60Init(const uint8_t *macaddr)
445 {
446 /* check CLKRDY bit to see if reset is complete */
447 /* The CLKRDY does not work. See Rev. B4 Silicon Errata point. Just wait. */
448 NextPacketPtr = RXSTART_INIT;
449 /* Rx start */
450 enc28j60Write(ERXSTL, RXSTART_INIT & 0xFF);
451 enc28j60Write(ERXSTH, RXSTART_INIT >> 8);
452 /* set receive pointer address */
453 enc28j60Write(ERXRDPTL, RXSTART_INIT & 0xFF);
454 enc28j60Write(ERXRDPTH, RXSTART_INIT >> 8);
455 /* RX end */
456 enc28j60Write(ERXNDL, RXSTOP_INIT & 0xFF);
457 enc28j60Write(ERXNDH, RXSTOP_INIT >> 8);
458 /* TX start */
459 enc28j60Write(ETXSTL, TXSTART_INIT & 0xFF);
460 enc28j60Write(ETXSTH, TXSTART_INIT >> 8);
461 /* TX end */
462 enc28j60Write(ETXNDL, TXSTOP_INIT & 0xFF);
463 enc28j60Write(ETXNDH, TXSTOP_INIT >> 8);
464
465 /* do bank 1 stuff, packet filter:
466 For broadcast packets we allow only ARP packtets
467 All other packets should be unicast only for our mac (MAADR) */
468 #if LWIP_IPV4 && LWIP_IPV6
469 enc28j60Write(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN | ERXFCON_MCEN);
470 enc28j60Write(EPMM0, 0x3f); /* ARP Pattern Match Filter */
471 enc28j60Write(EPMM1, 0x30);
472 enc28j60Write(EPMCSL, 0xf9);
473 enc28j60Write(EPMCSH, 0xf7);
474 #elif LWIP_IPV6
475 enc28j60Write(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_MCEN);
476 #else /* for IPv6 without ARP and BC */
477 enc28j60Write(ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_PMEN);
478 enc28j60Write(EPMM0, 0x3f); /* ARP Pattern Match Filter */
479 enc28j60Write(EPMM1, 0x30);
480 enc28j60Write(EPMCSL, 0xf9);
481 enc28j60Write(EPMCSH, 0xf7);
482 #endif
483 /* do bank 2 stuff */
484 /* enable MAC receive */
485 enc28j60Write(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
486 /* bring MAC out of reset */
487 enc28j60Write(MACON2, 0x00);
488 /* enable automatic padding to 60bytes and CRC operations */
489 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); /* MACON3_HFRMLEN */
490 /* set inter-frame gap (non-back-to-back) */
491 enc28j60Write(MAIPGL, 0x12);
492 enc28j60Write(MAIPGH, 0x0C);
493 /* set inter-frame gap (back-to-back) */
494 enc28j60Write(MABBIPG, 0x15);
495 /* Set the maximum packet size which the controller will accept */
496 /* Do not send packets longer than MAX_FRAMELEN: */
497 enc28j60Write(MAMXFLL, MAX_FRAMELEN & 0xFF);
498 enc28j60Write(MAMXFLH, MAX_FRAMELEN >> 8);
499
500 /* do bank 3 stuff */
501 /* write MAC address */
502 /* NOTE: MAC address in ENC28J60 is byte-backward */
503 enc28j60Write(MAADR5, macaddr[0]);
504 enc28j60Write(MAADR4, macaddr[1]);
505 enc28j60Write(MAADR3, macaddr[2]);
506 enc28j60Write(MAADR2, macaddr[3]);
507 enc28j60Write(MAADR1, macaddr[4]);
508 enc28j60Write(MAADR0, macaddr[5]);
509 enc28j60PhyWrite(PHCON1, 0, PHCON1_PDPXMD);
510
511 /* no loopback of transmitted frames */
512 enc28j60PhyWrite(PHCON2, 0, PHCON2_HDLDIS);
513
514 enc28j60PhyWrite(PHIE, 0, PHIE_PLNKIE | PHIE_PGEIE);
515
516 /* switch to bank 0 */
517 enc28j60SetBank(ECON1);
518 /* enable interrutps */
519 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_PKTIE | EIE_LINKIE | EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
520 /* enable packet reception */
521 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
522
523 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE);
524 }
525
526 /**
527 * set mac addr
528 * @param macaddr the macaddr for net
529 *
530 * @return
531 * - NULL
532 */
enc28j60Setmacaddr(const uint8_t * macaddr)533 static void enc28j60Setmacaddr(const uint8_t *macaddr)
534 {
535 ENC28J60_CSH();
536 /* enable MAC receive */
537 enc28j60Write(MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
538 /* bring MAC out of reset */
539 enc28j60Write(MACON2, 0x00);
540 /* enable automatic padding to 60bytes and CRC operations */
541 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FULDPX);
542
543 /* write MAC address */
544 /* NOTE: MAC address in ENC28J60 is byte-backward */
545 enc28j60Write(MAADR5, macaddr[0]);
546 enc28j60Write(MAADR4, macaddr[1]);
547 enc28j60Write(MAADR3, macaddr[2]);
548 enc28j60Write(MAADR2, macaddr[3]);
549 enc28j60Write(MAADR1, macaddr[4]);
550 enc28j60Write(MAADR0, macaddr[5]);
551
552 }
553
554 /**
555 * Hard reset enc28j60
556 * @param void
557 *
558 */
enc28j60hardreset(void)559 static void enc28j60hardreset(void)
560 {
561 gpio_pin_handle_t pin = NULL;
562 pin = csi_gpio_pin_initialize(PA1);
563 csi_gpio_pin_config(pin, GPIO_MODE_PULLNONE, GPIO_DIRECTION_OUTPUT);
564 csi_gpio_pin_write(pin, 0); /* LOW */
565 mdelay(3);
566 csi_gpio_pin_write(pin, 1);
567 mdelay(3);
568
569 printf("NET HARD RESET\n");
570 }
571
572 /**
573 * reset enc28j60
574 * @param obj the net work object
575 *
576 * @return
577 * - status
578 */
enc28j60Reset(int obj)579 static int enc28j60Reset(int obj)
580 {
581 int retry = 0;
582
583 ENC28J60_CSH();
584
585 if (obj == RST_ENC28J60_ALL) {
586 /* first net hard reset */
587 enc28j60hardreset();
588 enc28j60WriteOp(ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
589
590 while (!(enc28j60Read(ESTAT) & ESTAT_CLKRDY)) {
591 if (retry++ > 0xFFF) {
592 return -1;
593 }
594 }
595 } else if (obj == RST_ENC28J60_TX) {
596 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
597 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
598 } else if (obj == RST_ENC28J60_RX) {
599 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXRST);
600 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXRST);
601 }
602
603 return 0;
604 }
605
606 /**
607 * get rx free space
608 * @param void
609 *
610 * @return
611 * - status 0
612 */
enc28j60GetRxFreeSpace(void)613 static uint16_t enc28j60GetRxFreeSpace(void)
614 {
615 uint16_t free_space;
616 uint16_t erxrdpt;
617 uint16_t erxwrpt;
618
619 erxrdpt = enc28j60Read(ERXRDPTL);
620 erxrdpt |= enc28j60Read(ERXRDPTH) << 8;
621
622 erxwrpt = enc28j60Read(ERXWRPTL);
623 erxwrpt |= enc28j60Read(ERXWRPTH) << 8;
624
625 if (erxwrpt > erxrdpt) {
626 free_space = (RXSTOP_INIT - RXSTART_INIT) - (erxwrpt - erxrdpt);
627 } else if (erxwrpt == erxrdpt) {
628 free_space = (RXSTOP_INIT - RXSTART_INIT);
629 } else {
630 free_space = erxrdpt - erxwrpt - 1;
631 }
632
633 return free_space;
634 }
635
636 /**
637 * enc28j60 interrupt set
638 * @param interrupt_cb the interrupt callback function
639 *
640 * @return
641 * - status 0
642 */
643
enc28j60_set_interrupt(pin_t gpio_pin)644 static int enc28j60_set_interrupt(pin_t gpio_pin)
645 {
646 uint32_t ret = 0;
647
648 pin_int = csi_gpio_pin_initialize(gpio_pin);
649
650 ret = csi_gpio_pin_config(pin_int, GPIO_MODE_PULLUP, GPIO_DIRECTION_INPUT);
651
652 ret = csi_gpio_pin_irq_set(pin_int, GPIO_IRQ_MODE_LOW_LEVEL, 1);
653
654 return 0;
655 }
656
csi_eth_phy_get_version(eth_phy_handle_t handle)657 csi_drv_version_t csi_eth_phy_get_version(eth_phy_handle_t handle)
658 {
659 csi_drv_version_t version = {0xff, 0xff};
660 uint16_t dev_version, dev_version1;
661
662 if (handle == NULL) {
663 return version;
664 }
665
666 enc28j60Phyregread(PHHID1, 0, &dev_version);
667 enc28j60Phyregread(PHHID2, 0, &dev_version1);
668
669 version.api = CSI_ETH_PHY_API_VERSION;
670 version.drv = (dev_version << 16) + dev_version1;
671
672 return version;
673 }
674
csi_eth_phy_initialize(csi_eth_phy_read_t fn_read,csi_eth_phy_write_t fn_write)675 eth_phy_handle_t csi_eth_phy_initialize(csi_eth_phy_read_t fn_read, csi_eth_phy_write_t fn_write)
676 {
677 eth_phy_priv_t *phy_priv;
678
679 if ((fn_read == NULL) || (fn_write == NULL)) {
680 return NULL;
681 }
682
683 csi_gpio_port_initialize(0, (gpio_event_cb_t)enc28j60_int_handle);
684
685 phy_priv = &s_phy_instance[0];
686
687 phy_priv->phy_read = fn_read ;
688 phy_priv->phy_write = fn_write;
689
690 return (eth_mac_handle_t)phy_priv;
691 }
692
csi_eth_phy_uninitialize(eth_phy_handle_t handle)693 int32_t csi_eth_phy_uninitialize(eth_phy_handle_t handle)
694 {
695 if (handle == NULL) {
696 return -1;
697 }
698
699 return 0;
700 }
701
702
csi_eth_phy_deinit(void)703 int32_t csi_eth_phy_deinit(void)
704 {
705 /* no loopback of transmitted frames */
706 enc28j60PhyWrite(PHCON2, 0, PHCON2_HDLDIS);
707 /* LINK AND ALL PHY Interrupt Enable */
708 enc28j60PhyWrite(PHIE, 0, PHIE_PLNKIE | PHIE_PGEIE);
709 return 0;
710 }
711
csi_eth_phy_power_control(eth_phy_handle_t handle,eth_power_state_t state)712 int32_t csi_eth_phy_power_control(eth_phy_handle_t handle, eth_power_state_t state)
713 {
714 uint16_t power_control;
715
716 if (handle == NULL) {
717 return -1;
718 }
719
720 enc28j60Phyregread(PHCON1, 0, &power_control);
721
722 if (state == CSI_ETH_POWER_FULL) {
723 power_control &= ~(1 << 11);
724 } else if (state == CSI_ETH_POWER_OFF) {
725 power_control |= (1 << 11);
726 } else if (state == CSI_ETH_POWER_LOW) {
727
728 } else {
729 return -1;
730 }
731
732 enc28j60PhyWrite(PHCON1, 0, power_control);
733
734 return 0;
735 }
736
csi_eth_phy_set_interface(eth_phy_handle_t handle,uint32_t interface)737 int32_t csi_eth_phy_set_interface(eth_phy_handle_t handle, uint32_t interface)
738 {
739 if (handle == NULL) {
740 return -1;
741 }
742
743 return 0;
744 }
745
csi_eth_phy_get_linkinfo(eth_phy_handle_t handle)746 eth_link_info_t csi_eth_phy_get_linkinfo(eth_phy_handle_t handle)
747 {
748 eth_link_info_t net_link_info = {0};
749
750 if (handle == NULL) {
751 return net_link_info;
752 }
753
754 net_link_info.duplex = 1;
755 net_link_info.speed = 1;
756
757 return net_link_info;
758 }
759
csi_eth_phy_set_mode(eth_phy_handle_t handle,uint32_t mode)760 int32_t csi_eth_phy_set_mode(eth_phy_handle_t handle, uint32_t mode)
761 {
762 uint32_t phy_mode = 0;
763
764 if (handle == NULL) {
765 return -1;
766 }
767
768 eth_phy_priv_t *phy_priv = (eth_phy_priv_t *)handle;
769
770 phy_priv->link_info.speed = (mode & 0x03);
771 phy_priv->link_info.duplex = (mode & 0x04);
772 phy_priv->link_info.Loopback = (mode & 0x05);
773
774 if (phy_priv->link_info.duplex) {
775 phy_mode |= PHCON1_PDPXMD;
776 } else {
777 phy_mode &= ~(PHCON1_PDPXMD);
778 }
779
780 if (phy_priv->link_info.Loopback) {
781 phy_mode |= PHCON1_PLOOPBK;
782 } else {
783 phy_mode &= ~(PHCON1_PLOOPBK);
784 }
785
786 enc28j60PhyWrite(PHCON1, 0, phy_mode);
787
788 return 0;
789 }
790
csi_eth_phy_get_linkstate(eth_phy_handle_t handle)791 eth_link_state_t csi_eth_phy_get_linkstate(eth_phy_handle_t handle)
792 {
793 uint16_t phstat1;
794 uint16_t phstat2;
795 eth_link_state_t state;
796
797 if (handle == NULL) {
798 return -1;
799 }
800
801 uint8_t status = enc28j60Read(EIR);
802
803 if (status & EIR_LINKIF) {
804 /* as tested, need to read twice */
805 enc28j60Phyregread(PHSTAT1, 0, &phstat1);
806 enc28j60Phyregread(PHSTAT1, 0, &phstat2);
807
808 phstat1 |= phstat2;
809
810 if (phstat1 & 0x0004) {
811 state = ETH_LINK_UP;
812 } else {
813 state = ETH_LINK_DOWN;
814 }
815
816 /* resets to "0" when read */
817 enc28j60Phyregread(PHIR, 0, NULL);
818
819 return state;
820 }
821
822 return -1;
823 }
824
csi_eth_mac_initialize(eth_event_cb_t cb)825 eth_mac_handle_t csi_eth_mac_initialize(eth_event_cb_t cb)
826 {
827 eth_mac_priv_t *eth_priv;
828 static int eth_mac_init = 0;
829 int ret = -1;
830
831 if (cb == NULL) {
832 printf("cb == null\n");
833 return NULL;
834 }
835
836 eth_priv = &s_eth_instance[0];
837 eth_priv->cb_event = cb;
838
839 if (eth_mac_init == 0) {
840 //init spi get spi_handle
841 g_net_spi_hd = csi_spi_initialize(SPI1_TX, SPI1_RX, SPI1_CLK, SPI1_CS, (spi_event_cb_t)enc28j60_spi_transfer_callback, NULL);
842
843 //spi_handle success goto config spi
844 if (g_net_spi_hd != NULL) {
845
846 ret = csi_spi_config(g_net_spi_hd, SYSTEM_CLOCK, 2000000, SPI_MODE_MASTER, SPI_FORMAT_CPOL0_CPHA0,
847 SPI_ORDER_MSB2LSB, SPI_SS_MASTER_SW, 7);
848
849 pgpio_pin_handle1 = csi_gpio_pin_initialize(SPI1_CS);
850 csi_gpio_pin_config(pgpio_pin_handle1, GPIO_MODE_PULLNONE, GPIO_DIRECTION_OUTPUT);
851
852 }
853
854 eth_mac_init = 1;
855 }
856
857 if ((ret == 0) || (eth_mac_init == 1)) {
858
859 if (enc28j60Reset(RST_ENC28J60_ALL) == 0) {
860 printf("reset OK \n");
861 /* init enc28j60 module */
862 uint8_t macaddr[6];
863
864 csi_eth_mac_get_macaddr(NULL, (eth_mac_addr_t *)macaddr);
865
866 enc28j60Init(macaddr);
867
868 printf("enc28j60 init OK \n");
869 enc28j60_set_interrupt(PA5_A8);
870
871 //g_sem_spi_tx_hd = csi_kernel_sem_new(1, 0);
872 //g_sem_spi_rx_hd = csi_kernel_sem_new(1, 0);
873
874 return (eth_mac_handle_t)eth_priv;
875 }
876 }
877
878 return NULL;
879 }
880
csi_eth_mac_uninitialize(eth_mac_handle_t handle)881 int32_t csi_eth_mac_uninitialize(eth_mac_handle_t handle)
882 {
883 if (handle == NULL) {
884 return -1;
885 }
886
887 return 0;
888 }
889
csi_eth_mac_get_version(eth_mac_handle_t handle)890 csi_drv_version_t csi_eth_mac_get_version(eth_mac_handle_t handle)
891 {
892 csi_drv_version_t mac_version = {0xff, 0xff};
893
894 if (handle == NULL) {
895 return mac_version;
896 }
897
898 mac_version.api = CSI_ETH_PHY_API_VERSION;
899 mac_version.drv = enc28j60Read(EREVID);
900
901 return mac_version;
902 }
903
csi_eth_mac_power_control(eth_mac_handle_t handle,eth_power_state_t state)904 int32_t csi_eth_mac_power_control(eth_mac_handle_t handle, eth_power_state_t state)
905 {
906 uint8_t pw_control;
907
908 if (handle == NULL) {
909 return -1;
910 }
911
912 pw_control = enc28j60Read(ECON2);
913
914 if (state == CSI_ETH_POWER_FULL) {
915 pw_control &= ~(1 << 11);
916 } else if (state == CSI_ETH_POWER_LOW) {
917 pw_control |= (1 << 11);
918 } else if (state == CSI_ETH_POWER_OFF) {
919
920 } else {
921 return -1;
922 }
923
924 enc28j60Write(ECON2, pw_control);
925
926 return 0;
927 }
928
csi_eth_mac_get_macaddr(eth_mac_handle_t handle,eth_mac_addr_t * mac)929 int32_t csi_eth_mac_get_macaddr(eth_mac_handle_t handle, eth_mac_addr_t *mac)
930 {
931 if ((handle == NULL) || (mac == NULL)) {
932 return -1;
933 }
934
935 memcpy(mac, g_hw_addr, NET_HWADDR_LEN);
936 return 0;
937 }
938
csi_eth_mac_set_macaddr(eth_mac_handle_t handle,const eth_mac_addr_t * mac)939 int32_t csi_eth_mac_set_macaddr(eth_mac_handle_t handle, const eth_mac_addr_t *mac)
940 {
941 if ((handle == NULL) || (mac == NULL)) {
942 return -1;
943 }
944
945 memcpy(g_hw_addr, mac, NET_HWADDR_LEN);
946 printf("csiMAC: %02x:%02x:%02x:%02x:%02x:%02x\n", g_hw_addr[0], g_hw_addr[1], g_hw_addr[2],
947 g_hw_addr[3], g_hw_addr[4], g_hw_addr[5]);
948
949 enc28j60Setmacaddr(g_hw_addr);
950 return 0;
951 }
952
csi_eth_mac_set_addrfilter(eth_mac_handle_t handle,const eth_mac_addr_t * addr,uint32_t num_addr)953 int32_t csi_eth_mac_set_addrfilter(eth_mac_handle_t handle, const eth_mac_addr_t *addr, uint32_t num_addr)
954 {
955 if ((handle == NULL) || (addr == NULL)) {
956 return -1;
957 }
958
959 return 0;
960 }
961
csi_eth_mac_get_rx_framesize(eth_mac_handle_t handle)962 int32_t csi_eth_mac_get_rx_framesize(eth_mac_handle_t handle)
963 {
964 uint16_t len;
965 uint16_t rxstat;
966
967 if (handle == NULL) {
968 return -1;
969 }
970
971 /* check if a packet has been received and buffered
972 if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
973 The above does not work. See Rev. B4 Silicon Errata point 6. */
974 if (enc28j60Read(EPKTCNT) == 0) {
975 return (0);
976 }
977
978 /* Set the read pointer to the start of the received packet */
979 enc28j60Write(ERDPTL, (NextPacketPtr));
980 enc28j60Write(ERDPTH, (NextPacketPtr) >> 8);
981
982 /* read the next packet pointer */
983 NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
984 NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
985
986 /* read the packet length (see datasheet page 43) */
987 len = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
988 len |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
989 len -= 4; /* remove the CRC count */
990
991 /* limit retrieve length */
992 if (len > MAX_FRAMELEN - 1) {
993 printf("rx packet length is %d\n", len);
994 len = MAX_FRAMELEN - 1;
995 return -1;
996 }
997
998 /* read the receive status (see datasheet page 43) */
999 rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
1000 rxstat |= (uint16_t)enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
1001
1002 /* check CRC and symbol errors (see datasheet page 44, table 7-3): */
1003 /* The ERXFCON.CRCEN is set by default. Normally we should not */
1004 /* need to check this. */
1005 if ((rxstat & 0x80) == 0) {
1006 printf("rx status vector is 0x%x\n", rxstat);
1007 len = 0; // invalid
1008 return -1;
1009 }
1010
1011 return len;
1012 }
1013
csi_eth_mac_get_rx_frametime(eth_mac_handle_t handle,eth_mac_time_t * time)1014 int32_t csi_eth_mac_get_rx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time)
1015 {
1016 if ((handle == NULL)) {
1017 return -1;
1018 }
1019
1020 return 0;
1021 }
1022
csi_eth_mac_get_tx_frametime(eth_mac_handle_t handle,eth_mac_time_t * time)1023 int32_t csi_eth_mac_get_tx_frametime(eth_mac_handle_t handle, eth_mac_time_t *time)
1024 {
1025 if (handle == NULL) {
1026 return -1;
1027 }
1028
1029 return 0;
1030 }
1031
csi_eth_mac_control(eth_mac_handle_t handle,uint32_t control,uint32_t arg)1032 int32_t csi_eth_mac_control(eth_mac_handle_t handle, uint32_t control, uint32_t arg)
1033 {
1034 if (handle == NULL) {
1035 return -1;
1036 }
1037
1038
1039 if (control == CSI_ETH_MAC_CONTROL_RX) {
1040 if (arg) {
1041 //enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, EIE, EIE_INTIE);
1042 csi_gpio_pin_irq_set(pin_int, GPIO_IRQ_MODE_LOW_LEVEL, 1);
1043
1044 } else {
1045 //enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, EIE, EIE_INTIE);
1046 csi_gpio_pin_irq_set(pin_int, GPIO_IRQ_MODE_LOW_LEVEL, 0);
1047 }
1048
1049 return 0;
1050 }
1051
1052 return 0;
1053 }
1054
1055 /**
1056 * send a packet data
1057 * @param address the packet data length
1058 *
1059 * @return
1060 * - sent data length
1061 */
csi_eth_mac_send_frame(eth_mac_handle_t handle,const uint8_t * frame,uint32_t len,uint32_t flags)1062 int32_t csi_eth_mac_send_frame(eth_mac_handle_t handle, const uint8_t *frame, uint32_t len, uint32_t flags)
1063 {
1064 int retry = 0;
1065
1066 if ((handle == NULL) || (frame == NULL)) {
1067 return -1;
1068 }
1069
1070 if (len > MAX_FRAMELEN) {
1071 printf("TX len %d is too large to send\n", len);
1072 return 0;
1073 }
1074
1075 while (enc28j60Read(ECON1) & ECON1_TXRTS) {
1076 if (retry++ > 0xFFF) {
1077 printf("data not be sent out\n");
1078 return -1;
1079 }
1080 }
1081
1082 /* Set the write pointer to start of transmit buffer area */
1083 enc28j60Write(EWRPTL, TXSTART_INIT & 0xFF);
1084 enc28j60Write(EWRPTH, TXSTART_INIT >> 8);
1085
1086 /* Set the TXND pointer to correspond to the packet size given */
1087 /* Status vector will be written at ETXND+1. */
1088 enc28j60Write(ETXNDL, (TXSTART_INIT + len) & 0xFF);
1089 enc28j60Write(ETXNDH, (TXSTART_INIT + len) >> 8);
1090
1091 /* write per-packet control byte (0x00 means use macon3 settings) */
1092 enc28j60WriteOp(ENC28J60_WRITE_BUF_MEM, 0, 0x00);
1093
1094 /* copy the packet into the transmit buffer */
1095 enc28j60WriteBuffer(len, (uint8_t *)frame);
1096
1097 /* send the contents of the transmit buffer onto the network */
1098 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
1099
1100 /* Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12. */
1101 if ((enc28j60Read(EIR) & EIR_TXERIF)) {
1102 enc28j60WriteOp(ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRTS);
1103 }
1104
1105 return len;
1106 }
1107
csi_eth_mac_read_frame(eth_mac_handle_t handle,uint8_t * frame,uint32_t len)1108 int32_t csi_eth_mac_read_frame(eth_mac_handle_t handle, uint8_t *frame, uint32_t len)
1109 {
1110 uint32_t rlen;
1111 uint16_t rxstat;
1112
1113 if ((handle == NULL) || (frame == NULL)) {
1114 return -1;
1115 }
1116
1117 /* check if a packet has been received and buffered
1118 if( !(enc28j60Read(EIR) & EIR_PKTIF) ){
1119 The above does not work. See Rev. B4 Silicon Errata point 6. */
1120 if (enc28j60Read(EPKTCNT) == 0) {
1121 return (0);
1122 }
1123
1124 /* Set the read pointer to the start of the received packet */
1125 enc28j60Write(ERDPTL, (NextPacketPtr));
1126 enc28j60Write(ERDPTH, (NextPacketPtr) >> 8);
1127
1128 /* read the next packet pointer */
1129 NextPacketPtr = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
1130 NextPacketPtr |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
1131
1132 /* read the packet length (see datasheet page 43) */
1133 rlen = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
1134 rlen |= enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
1135 rlen -= 4; /* remove the CRC count */
1136
1137 /* limit retrieve length */
1138 if (rlen > MAX_FRAMELEN - 1) {
1139 printf("rx packet length is %d\n", rlen);
1140 rlen = MAX_FRAMELEN - 1;
1141 return -1;
1142 }
1143
1144 /* read the receive status (see datasheet page 43) */
1145 rxstat = enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0);
1146 rxstat |= (uint16_t)enc28j60ReadOp(ENC28J60_READ_BUF_MEM, 0) << 8;
1147
1148 /* check CRC and symbol errors (see datasheet page 44, table 7-3): */
1149 /* The ERXFCON.CRCEN is set by default. Normally we should not */
1150 /* need to check this. */
1151 if ((rxstat & 0x80) == 0) {
1152 printf("rx status vector is 0x%x\n", rxstat);
1153 rlen = 0; // invalid
1154 return -1;
1155 }
1156
1157 /* copy the packet from the receive buffer */
1158 enc28j60ReadBuffer(rlen, frame);
1159
1160 /* Move the RX read pointer to the start of the next received packet */
1161 /* This frees the memory we just read out */
1162 enc28j60Write(ERXRDPTL, (NextPacketPtr));
1163 enc28j60Write(ERXRDPTH, (NextPacketPtr) >> 8);
1164
1165 /* decrement the packet counter indicate we are done with this packet */
1166 enc28j60WriteOp(ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC | ECON2_PKTDEC);
1167
1168 return rlen;
1169
1170 }
1171
csi_eth_mac_get_capabilities(eth_mac_handle_t handle)1172 eth_capabilities_t csi_eth_mac_get_capabilities(eth_mac_handle_t handle)
1173 {
1174 eth_capabilities_t capab = {0};
1175
1176 if (handle == NULL) {
1177 return capab;
1178 }
1179
1180 eth_mac_priv_t *mac_priv = (eth_mac_priv_t *)handle;
1181
1182 mac_priv->capabilities.mac_address = 1;
1183
1184 capab = mac_priv->capabilities;
1185
1186 return capab;
1187 }
1188
csi_eth_mac_signal_event(eth_mac_handle_t handle,uint32_t event)1189 void csi_eth_mac_signal_event(eth_mac_handle_t handle, uint32_t event)
1190 {
1191 if (handle == NULL) {
1192 return;
1193 }
1194
1195 }
1196
csi_eth_mac_control_time(eth_mac_handle_t handle,uint32_t control,eth_mac_time_t * time)1197 int32_t csi_eth_mac_control_time(eth_mac_handle_t handle, uint32_t control, eth_mac_time_t *time)
1198 {
1199 if (handle == NULL) {
1200 return -1;
1201 }
1202
1203 return 0;
1204 }
1205
csi_eth_mac_phy_read(eth_mac_handle_t handle,uint8_t phy_addr,uint8_t reg_addr,uint16_t * data)1206 int32_t csi_eth_mac_phy_read(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data)
1207 {
1208 if ((handle == NULL) || (data == NULL)) {
1209 return -1;
1210 }
1211
1212 return 0;
1213 }
1214
csi_eth_mac_phy_write(eth_mac_handle_t handle,uint8_t phy_addr,uint8_t reg_addr,uint16_t data)1215 int32_t csi_eth_mac_phy_write(eth_mac_handle_t handle, uint8_t phy_addr, uint8_t reg_addr, uint16_t data)
1216 {
1217 if ((handle == NULL)) {
1218 return -1;
1219 }
1220
1221 return 0;
1222 }
1223
csi_eth_mac_add_framefilter(eth_mac_handle_t handle,const eth_frame_filter_t * filter)1224 int32_t csi_eth_mac_add_framefilter(eth_mac_handle_t handle, const eth_frame_filter_t *filter)
1225 {
1226 if ((handle == NULL) || (filter == NULL)) {
1227 return -1;
1228 }
1229
1230 return 0;
1231 }
1232
csi_eth_mac_remove_framefilter(eth_mac_handle_t handle,uint32_t filter_id)1233 int32_t csi_eth_mac_remove_framefilter(eth_mac_handle_t handle, uint32_t filter_id)
1234 {
1235 if (handle == NULL) {
1236 return -1;
1237 }
1238
1239 return 0;
1240 }
1241
csi_eth_mac_en_framefilter(eth_mac_handle_t handle,uint32_t filter_id,bool en)1242 int32_t csi_eth_mac_en_framefilter(eth_mac_handle_t handle, uint32_t filter_id, bool en)
1243 {
1244 if (handle == NULL) {
1245 return -1;
1246 }
1247
1248 return 0;
1249 }
1250
csi_eth_mac_get_framefilter(eth_mac_handle_t handle,eth_frame_filter_list_t * list,uint32_t * count_out,uint32_t max_count)1251 int32_t csi_eth_mac_get_framefilter(eth_mac_handle_t handle, eth_frame_filter_list_t *list, uint32_t *count_out, uint32_t max_count)
1252 {
1253 if ((handle == NULL) || (list == NULL)) {
1254 return -1;
1255 }
1256
1257 return 0;
1258 }
1259
1260