1 /*
2 * This is a generated file
3 *
4 * Copyright 2021 QuickLogic
5 *
6 * Licensed under the Apache License, Version 2.0 (the "License");
7 * you may not use this file except in compliance with the License.
8 * You may obtain a copy of the License at
9 *
10 * http://www.apache.org/licenses/LICENSE-2.0
11 *
12 * Unless required by applicable law or agreed to in writing, software
13 * distributed under the License is distributed on an "AS IS" BASIS,
14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15 * See the License for the specific language governing permissions and
16 * limitations under the License.
17 *
18 * SPDX-License-Identifier: Apache-2.0
19 */
20
21 #ifndef __UDMA_SDIO_H_
22 #define __UDMA_SDIO_H_
23
24 //---------------------------------//
25 //
26 // Module: UDMA_SDIO
27 //
28 //---------------------------------//
29
30 #ifndef __IO
31 #define __IO volatile
32 #endif
33
34 #ifndef __I
35 #define __I volatile
36 #endif
37
38 #ifndef __O
39 #define __O volatile
40 #endif
41
42 #include "stdint.h"
43
44 typedef struct {
45
46 // Offset = 0x0000
47 union {
48 __IO uint32_t rx_saddr;
49 struct {
50 __IO uint32_t saddr : 32; // 21 localparam L2_AWIDTH_NOAL = L2_ADDR_WIDTH + 2;
51 } rx_saddr_b;
52 };
53
54 // Offset = 0x0004
55 union {
56 __IO uint32_t rx_size;
57 struct {
58 __IO uint32_t size : 20;//16; //should be 20 bit. udma 1MB addressing.
59 } rx_size_b;
60 };
61
62 // Offset = 0x0008
63 union {
64 __IO uint32_t rx_cfg;
65 struct {
66 __IO uint32_t continuous : 1;
67 __IO uint32_t datasize : 2;
68 __IO uint32_t : 1;
69 __IO uint32_t en : 1;
70 //__IO uint32_t pending : 1;
71 __IO uint32_t clr : 1;
72 } rx_cfg_b;
73 };
74 __I uint32_t unused0[1];
75
76 // Offset = 0x0010
77 union {
78 __IO uint32_t tx_saddr;
79 struct {
80 __IO uint32_t saddr : 12;
81 } tx_saddr_b;
82 };
83
84 // Offset = 0x0014
85 union {
86 __IO uint32_t tx_size;
87 struct {
88 __IO uint32_t size : 16;
89 } tx_size_b;
90 };
91
92 // Offset = 0x0018
93 union {
94 __IO uint32_t tx_cfg;
95 struct {
96 __IO uint32_t continuous : 1;
97 __IO uint32_t datasize : 2;
98 __IO uint32_t : 1;
99 __IO uint32_t en : 1;
100 //__IO uint32_t pending : 1;
101 __IO uint32_t clr : 1;
102 } tx_cfg_b;
103 };
104 __I uint32_t unused1[1];
105
106 // Offset = 0x0020
107 union {
108 __IO uint32_t cmd_op;
109 struct {
110 __IO uint32_t cmd_rsp_type : 3;
111 __IO uint32_t : 5;
112 __IO uint32_t cmd_op : 6;
113 } cmd_op_b;
114 };
115
116 // Offset = 0x0024
117 union {
118 __IO uint32_t cmd_arg;
119 struct {
120 __IO uint32_t cmd_arg : 32;
121 } cmd_arg_b;
122 };
123
124 // Offset = 0x0028
125 union {
126 __IO uint32_t data_setup;
127 struct {
128 __IO uint32_t data_en : 1;
129 __IO uint32_t data_rwn : 1;
130 __IO uint32_t data_quad : 1;
131 __IO uint32_t : 5;
132 __IO uint32_t block_num : 8;
133 __IO uint32_t block_size : 10;
134 } data_setup_b;
135 };
136
137 // Offset = 0x002c
138 union {
139 __IO uint32_t start;
140 struct {
141 __IO uint32_t start : 1;
142 } start_b;
143 };
144
145 // Offset = 0x0030
146 union {
147 __IO uint32_t rsp0;
148 struct {
149 __IO uint32_t rsp0 : 32;
150 } rsp0_b;
151 };
152
153 // Offset = 0x0034
154 union {
155 __IO uint32_t rsp1;
156 struct {
157 __IO uint32_t rsp1 : 32;
158 } rsp1_b;
159 };
160
161 // Offset = 0x0038
162 union {
163 __IO uint32_t rsp2;
164 struct {
165 __IO uint32_t rsp2 : 32;
166 } rsp2_b;
167 };
168
169 // Offset = 0x003c
170 union {
171 __IO uint32_t rsp3;
172 struct {
173 __IO uint32_t rsp3 : 32;
174 } rsp3_b;
175 };
176
177 // Offset = 0x0040
178 union {
179 __IO uint32_t clk_div;
180 struct {
181 __IO uint32_t clk_div : 8;
182 __IO uint32_t valid : 1;
183 } clk_div_b;
184 };
185
186 // Offset = 0x0044
187 union {
188 __IO uint32_t status;
189 struct {
190 __IO uint32_t eot : 1;
191 __IO uint32_t error : 1;
192 __IO uint32_t : 14;
193 __IO uint32_t cmd_err_status : 6;
194 } status_b;
195 };
196 } UdmaSdio_t;
197
198
199 #define REG_RX_SADDR 0x00
200 #define REG_RX_SADDR_SADDR_LSB 0
201 #define REG_RX_SADDR_SADDR_MASK 0xffffffff
202 #define REG_RX_SIZE 0x04
203 #define REG_RX_SIZE_SIZE_LSB 0
204 #define REG_RX_SIZE_SIZE_MASK 0xffff
205 #define REG_RX_CFG 0x08
206 #define REG_RX_CFG_CLR_LSB 5
207 #define REG_RX_CFG_CLR_MASK 0x1
208 #define REG_RX_CFG_PENDING_LSB 5
209 #define REG_RX_CFG_PENDING_MASK 0x1
210 #define REG_RX_CFG_EN_LSB 4
211 #define REG_RX_CFG_EN_MASK 0x1
212 #define REG_RX_CFG_DATASIZE_LSB 1
213 #define REG_RX_CFG_DATASIZE_MASK 0x3
214 #define REG_RX_CFG_CONTINUOUS_LSB 0
215 #define REG_RX_CFG_CONTINUOUS_MASK 0x1
216 #define REG_TX_SADDR 0x10
217 #define REG_TX_SADDR_SADDR_LSB 0
218 #define REG_TX_SADDR_SADDR_MASK 0xfff
219 #define REG_TX_SIZE 0x14
220 #define REG_TX_SIZE_SIZE_LSB 0
221 #define REG_TX_SIZE_SIZE_MASK 0xffff
222 #define REG_TX_CFG 0x18
223 #define REG_TX_CFG_CLR_LSB 5
224 #define REG_TX_CFG_CLR_MASK 0x1
225 #define REG_TX_CFG_PENDING_LSB 5
226 #define REG_TX_CFG_PENDING_MASK 0x1
227 #define REG_TX_CFG_EN_LSB 4
228 #define REG_TX_CFG_EN_MASK 0x1
229 #define REG_TX_CFG_DATASIZE_LSB 1
230 #define REG_TX_CFG_DATASIZE_MASK 0x3
231 #define REG_TX_CFG_CONTINUOUS_LSB 0
232 #define REG_TX_CFG_CONTINUOUS_MASK 0x1
233 #define REG_CMD_OP 0x20
234 #define REG_CMD_OP_CMD_OP_LSB 8
235 #define REG_CMD_OP_CMD_OP_MASK 0x3f
236 #define REG_CMD_OP_CMD_RSP_TYPE_LSB 0
237 #define REG_CMD_OP_CMD_RSP_TYPE_MASK 0x7
238 #define REG_CMD_ARG 0x24
239 #define REG_CMD_ARG_CMD_ARG_LSB 0
240 #define REG_CMD_ARG_CMD_ARG_MASK 0xffffffff
241 #define REG_DATA_SETUP 0x28
242 #define REG_DATA_SETUP_BLOCK_SIZE_LSB 16
243 #define REG_DATA_SETUP_BLOCK_SIZE_MASK 0x3ff
244 #define REG_DATA_SETUP_BLOCK_NUM_LSB 8
245 #define REG_DATA_SETUP_BLOCK_NUM_MASK 0xff
246 #define REG_DATA_SETUP_DATA_QUAD_LSB 2
247 #define REG_DATA_SETUP_DATA_QUAD_MASK 0x1
248 #define REG_DATA_SETUP_DATA_RWN_LSB 1
249 #define REG_DATA_SETUP_DATA_RWN_MASK 0x1
250 #define REG_DATA_SETUP_DATA_EN_LSB 0
251 #define REG_DATA_SETUP_DATA_EN_MASK 0x1
252 #define REG_START 0x2C
253 #define REG_START_START_LSB 0
254 #define REG_START_START_MASK 0x1
255 #define REG_RSP0 0x30
256 #define REG_RSP0_RSP0_LSB 0
257 #define REG_RSP0_RSP0_MASK 0xffffffff
258 #define REG_RSP1 0x34
259 #define REG_RSP1_RSP1_LSB 0
260 #define REG_RSP1_RSP1_MASK 0xffffffff
261 #define REG_RSP2 0x38
262 #define REG_RSP2_RSP2_LSB 0
263 #define REG_RSP2_RSP2_MASK 0xffffffff
264 #define REG_RSP3 0x3C
265 #define REG_RSP3_RSP3_LSB 0
266 #define REG_RSP3_RSP3_MASK 0xffffffff
267 #define REG_CLK_DIV 0x40
268 #define REG_CLK_DIV_VALID_LSB 8
269 #define REG_CLK_DIV_VALID_MASK 0x1
270 #define REG_CLK_DIV_CLK_DIV_LSB 0
271 #define REG_CLK_DIV_CLK_DIV_MASK 0xff
272 #define REG_STATUS 0x44
273 #define REG_STATUS_CMD_ERR_STATUS_LSB 16
274 #define REG_STATUS_CMD_ERR_STATUS_MASK 0x3f
275 #define REG_STATUS_ERROR_LSB 1
276 #define REG_STATUS_ERROR_MASK 0x1
277 #define REG_STATUS_EOT_LSB 0
278 #define REG_STATUS_EOT_MASK 0x1
279
280 #ifndef __REGFIELD_OPS_
281 #define __REGFIELD_OPS_
regfield_read(uint32_t reg,uint32_t mask,uint32_t lsb)282 static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
283 return (reg >> lsb) & mask;
284 }
regfield_write(uint32_t reg,uint32_t mask,uint32_t lsb,uint32_t value)285 static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
286 reg &= ~(mask << lsb);
287 reg |= (value & mask) << lsb;
288 return reg;
289 }
290 #endif // __REGFIELD_OPS_
291
292 #endif // __UDMA_SDIO_H_
293