1 //***************************************************************************** 2 // 3 // hw_usb.h - Macros for use in accessing the USB registers. 4 // 5 // Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved. 6 // Software License Agreement 7 // 8 // Texas Instruments (TI) is supplying this software for use solely and 9 // exclusively on TI's microcontroller products. The software is owned by 10 // TI and/or its suppliers, and is protected under applicable copyright 11 // laws. You may not combine this software with "viral" open-source 12 // software in order to form a larger program. 13 // 14 // THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS. 15 // NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT 16 // NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 17 // A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY 18 // CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 19 // DAMAGES, FOR ANY REASON WHATSOEVER. 20 // 21 // This is part of Hercules Development Kit software. 22 // 23 //****************************************************************************** 24 25 #ifndef __HW_USB_H__ 26 #define __HW_USB_H__ 27 28 /** @brief Base address of memmory mapped Registers */ 29 #define USBD_0_BASE 0xFCF78A00u 30 #define USB0_BASE USBD_0_BASE 31 32 typedef volatile struct { 33 uint16 rev; /* Revision */ 34 35 /** Endpoint registers ***************************************************/ 36 uint16 epnum; /* Endpoint selection */ 37 uint16 data; /* Data */ 38 uint16 ctrl; /* Control */ 39 uint16 stat_flag; /* Status */ 40 uint16 rxf_stat; /* RX FIFO Status */ 41 uint16 syscon1; /* System configuration 1 */ 42 uint16 syscon2; /* System configuration 2 */ 43 uint16 dev_stat; /* Device status */ 44 uint16 sof; /* Start of frame */ 45 uint16 irq_en; /* Interrupt enable */ 46 uint16 dma_irqen; /* DMA Interrupt enable */ 47 uint16 irqsrc; /* Interrupt source */ 48 uint16 epn_stat; /* Non-ISO EP interrupt enable */ 49 uint16 dman_stat; /* Non-ISO DMA interrupt enable */ 50 uint16 _rsvd1[1]; /* Reserved for reg holes */ 51 52 /** DMA Configuration ***************************************************/ 53 uint16 rxdma_cfg; /* DMA Rx channels configuration */ 54 uint16 txdma_cfg; /* DMA Tx channels configuration */ 55 uint16 data_dma; /* DMA FIFO data */ 56 uint16 txdma0; /* Transmit DMA control 0 */ 57 uint16 txdma1; /* Transmit DMA control 1 */ 58 uint16 txdma2; /* Transmit DMA control 2 */ 59 uint16 _rsvd2[2]; /* Reserved for reg holes */ 60 61 uint16 dman_rxdma0; /* Receive DMA control 0 */ 62 uint16 dman_rxdma1; /* Receive DMA control 1 */ 63 uint16 dman_rxdma2; /* Receive DMA control 2 */ 64 uint16 _rsvd3[5]; /* Reserved */ 65 66 /** Endpoint Configuration ***********************************************/ 67 uint16 ep0; /* Endpoint 0 Configuration */ 68 69 uint16 epn_rx[15]; /* RX EP configurations... */ 70 uint16 _rsvd4[1]; /* Reserved for reg holes */ 71 72 uint16 epn_tx[15]; /* TX EP configurations... */ 73 } usbdRegs; 74 75 /******************************************************************************\ 76 * Register Bit Masks 77 * (USBD_<Instance ID=0>_<Register Name>_<Bit Field Name> <Mask Value> 78 \******************************************************************************/ 79 80 /* Endpoint selection *********************************************************/ 81 #define USBD_EP_NUM_SETUP_SEL (0x0040u) 82 #define USBD_EP_NUM_EP_SEL (0x0020u) 83 #define USBD_EP_NUM_EP_DIR (0x0010u) 84 #define USBD_EP_NUM_EP_NUM_MASK (0x000Fu) 85 86 /* Data ***********************************************************************/ 87 #define USBD_DATA_DATA (0xFFFFu) 88 89 /* Control ********************************************************************/ 90 #define USBD_CTRL_CLR_HALT (0x0080u) 91 #define USBD_CTRL_SET_HALT (0x0040u) 92 #define USBD_CTRL_SET_FIFO_EN (0x0004u) 93 #define USBD_CTRL_CLR_EP (0x0002u) 94 #define USBD_CTRL_RESET_EP (0x0001u) 95 96 /* Status *********************************************************************/ 97 #define USBD_STAT_FLG_NO_RXPACKET (0x8000u) 98 #define USBD_STAT_FLG_MISS_IN (0x4000u) 99 #define USBD_STAT_FLG_DATA_FLUSH (0x2000u) 100 #define USBD_STAT_FLG_ISO_ERR (0x1000u) 101 #define USBD_STAT_FLG_ISO_FIFO_EMPTY (0x0200u) 102 #define USBD_STAT_FLG_ISO_FIFO_FULL (0x0100u) 103 #define USBD_STAT_FLG_EP_HALTED (0x0040u) 104 #define USBD_STAT_FLG_STALL (0x0020u) 105 #define USBD_STAT_FLG_NAK (0x0010u) 106 #define USBD_STAT_FLG_ACK (0x0008u) 107 #define USBD_STAT_FLG_FIFO_EN (0x0004u) 108 #define USBD_STAT_FLG_NON_ISO_FIFO_EMPTY (0x0002u) 109 #define USBD_STAT_FLG_NON_ISO_FIFO_FULL (0x0001u) 110 111 /* RX FIFO Status */ 112 #define USBD_RXFSTAT_RXF_COUNT (0x03FFu) 113 114 /* System configuration 1 *****************************************************/ 115 #define USBD_SYSCON1_CFG_LOCK (0x0100u) 116 #define USBD_SYSCON1_DATA_ENDIAN (0x0080u) 117 #define USBD_SYSCON1_DMA_ENDIAN (0x0040u) 118 #define USBD_SYSCON1_NAK_EN (0x0010u) 119 #define USBD_SYSCON1_AUTODEC_DIS (0x0008u) 120 #define USBD_SYSCON1_SELF_PWR (0x0004u) 121 #define USBD_SYSCON1_SOFF_DIS (0x0002u) 122 #define USBD_SYSCON1_PULLUP_EN (0x0001u) 123 124 /* System configuration 2 *****************************************************/ 125 #define USBD_SYSCON2_RMT_WKP (0x0040u) 126 #define USBD_SYSCON2_STALL_CMD (0x0020u) 127 #define USBD_SYSCON2_DEV_CFG (0x0008u) 128 #define USBD_SYSCON2_CLR_CFG (0x0004u) 129 130 /* Device status **************************************************************/ 131 #define USBD_DEVSTAT_B_HNP_ENABLE (0x0200u) 132 #define USBD_DEVSTAT_A_HNP_SUPPORT (0x0100u) 133 #define USBD_DEVSTAT_A_ALT_HNP_SUPPORT (0x0080u) 134 #define USBD_DEVSTAT_R_WK_OK (0x0040u) 135 #define USBD_DEVSTAT_USB_RESET (0x0020u) 136 #define USBD_DEVSTAT_SUS (0x0010u) 137 #define USBD_DEVSTAT_CFG (0x0008u) 138 #define USBD_DEVSTAT_ADD (0x0004u) 139 #define USBD_DEVSTAT_DEF (0x0002u) 140 #define USBD_DEVSTAT_ATT (0x0001u) 141 142 143 /* Start of frame *************************************************************/ 144 #define USBD_SOF_FT_LOCK (0x1000u) 145 #define USBD_SOF_TS_OK (0x0800u) 146 #define USBD_SOF_TS (0x07FFu) 147 148 /* Interrupt enable ***********************************************************/ 149 #define USBD_IRQ_EN_SOF_IE (0x0080u) 150 #define USBD_IRQ_EN_EPN_RX_IE (0x0020u) 151 #define USBD_IRQ_EN_EPN_TX_IE (0x0010u) 152 #define USBD_IRQ_EN_DS_CHG_IE (0x0008u) 153 #define USBD_IRQ_EN_EP0_IE (0x0001u) 154 155 /* DMA Interrupt enable *******************************************************/ 156 #define USBD_DMA_IRQ_EN_TX2_DONE_IE (0x0400u) 157 #define USBD_DMA_IRQ_EN_RX2_CNT_IE (0x0200u) 158 #define USBD_DMA_IRQ_EN_RX2_EOT_IE (0x0100u) 159 #define USBD_DMA_IRQ_EN_TX1_DONE_IE (0x0040u) 160 #define USBD_DMA_IRQ_EN_RX1_CNT_IE (0x0020u) 161 #define USBD_DMA_IRQ_EN_RX1_EOT_IE (0x0010u) 162 #define USBD_DMA_IRQ_EN_TX0_DONE_IE (0x0004u) 163 #define USBD_DMA_IRQ_EN_RX0_CNT_IE (0x0002u) 164 #define USBD_DMA_IRQ_EN_RX0_EOT_IE (0x0001u) 165 166 /* Interrupt source ***********************************************************/ 167 #define USBD_IRQ_SRC_TXN_DONE (0x0400u) 168 #define USBD_IRQ_SRC_RXN_CNT (0x0200u) 169 #define USBD_IRQ_SRC_RXN_EOT (0x0100u) 170 #define USBD_IRQ_SRC_SOF (0x0080u) 171 #define USBD_IRQ_SRC_EPN_RX (0x0020u) 172 #define USBD_IRQ_SRC_EPN_TX (0x0010u) 173 #define USBD_IRQ_SRC_DS_CHG (0x0008u) 174 #define USBD_IRQ_SRC_SETUP (0x0004u) 175 #define USBD_IRQ_SRC_EP0_RX (0x0002u) 176 #define USBD_IRQ_SRC_EP0_TX (0x0001u) 177 178 /* Non-ISO endpoint interrupt enable ******************************************/ 179 #define USBD_EPN_STAT_RX_IT_SRC (0x0F00u) 180 #define USBD_EPN_STAT_TX_IT_SRC (0x000Fu) 181 182 /* Non-ISO DMA interrupt enable ***********************************************/ 183 #define USBD_DMAN_STAT_RX_SB (0x1000u) 184 #define USBD_DMAN_STAT_RX_IT_SRC (0x0F00u) 185 #define USBD_DMAN_STAT_TX_IT_SRC (0x000Fu) 186 187 /* DMA Receive channels configuration *****************************************/ 188 #define USBD_RXDMA_CFG_RX_REQ (0x1000u) 189 #define USBD_RXDMA_CFG_RXDMA2_EP (0x0F00u) 190 #define USBD_RXDMA_CFG_RXDMA1_EP (0x00F0u) 191 #define USBD_RXDMA_CFG_RXDMA0_EP (0x000Fu) 192 193 /* DMA Transmit channels configuration ****************************************/ 194 #define USBD_TXDMA_CFG_TX_REQ (0x1000u) 195 #define USBD_TXDMA_CFG_TXDMA2_EP (0x0F00u) 196 #define USBD_TXDMA_CFG_TXDMA1_EP (0x00F0u) 197 #define USBD_TXDMA_CFG_TXDMA0_EP (0x000Fu) 198 199 /* DMA FIFO data **************************************************************/ 200 #define USBD_DATA_DMA_DATA_DMA (0xFFFFu) 201 202 /* Transmit DMA control 0 *****************************************************/ 203 #define USBD_TXDMA0_TX0_EOT (0x8000u) 204 #define USBD_TXDMA0_TX0_START (0x4000u) 205 #define USBD_TXDMA0_TX0_TSC (0x03FFu) 206 207 /* Transmit DMA control 1 *****************************************************/ 208 #define USBD_TXDMA1_TX1_EOT (0x8000u) 209 #define USBD_TXDMA1_TX1_START (0x4000u) 210 #define USBD_TXDMA1_TX1_TSC (0x03FFu) 211 #define USBD_TXDMA1_TX1_TSC_SHIFT (0x0000u) 212 213 /* Transmit DMA control 2 *****************************************************/ 214 #define USBD_TXDMA2_TX2_EOT (0x8000u) 215 #define USBD_TXDMA2_TX2_START (0x4000u) 216 #define USBD_TXDMA2_TX2_TSC (0x03FFu) 217 218 /* Receive DMA control 0 ******************************************************/ 219 #define USBD_RXDMA0_RX0_STOP (0x8000u) 220 #define USBD_RXDMA0_RX0_TC (0x00FFu) 221 222 /* Receive DMA control 1 ******************************************************/ 223 #define USBD_RXDMA1_RX10_STOP (0x8000u) 224 #define USBD_RXDMA1_RX1_TC (0x00FFu) 225 226 /* Receive DMA control 2 ******************************************************/ 227 #define USBD_RXDMA2_RX2_STOP (0x8000u) 228 #define USBD_RXDMA2_RX2_TC (0x00FFu) 229 230 /* Endpoint 0 Configuration ***************************************************/ 231 #define USBD_EP0_SIZE (0x3000u) 232 #define USBD_EP0_PTR (0x07FFu) 233 234 /* Receive endpoint configurations... *****************************************/ 235 #define USBD_RX_EP_VALID (0x8000u) 236 #define USBD_RX_EP_SIZEDB (0x4000u) 237 #define USBD_RX_EP_SIZE (0x3000u) 238 #define USBD_RX_EP_ISO (0x0800u) 239 #define USBD_RX_EP_PTR (0x07FFu) 240 241 /* Transmit endpoint configurations... ****************************************/ 242 #define USBD_TX_EP_VALID (0x8000u) 243 #define USBD_TX_EP_SIZEDB (0x4000u) 244 #define USBD_TX_EP_SIZE (0x3000u) 245 #define USBD_TX_EP_ISO (0x0800u) 246 #define USBD_TX_EP_PTR (0x07FFu) 247 248 #define USBD_MAX_EP0_PTR (0xFFu) 249 #define USBD_EP_RX_MAX (15u) 250 #define USBD_EP_TX_MAX (15u) 251 252 /** @brief Macro for setting a bit/s in a register (read, modify & write) */ 253 #define USBD_REG_BIT_SET(reg,bit) ((reg) |= ((uint16)(bit))) 254 /** @brief Macro for clearing a bit/s in a register (read, modify & write) */ 255 #define USBD_REG_BIT_CLR(reg,bit) ((reg) &= ((uint16)~((uint16)bit))) 256 /** @brief Macro for setting a bit/s in a register (write) */ 257 #define USBD_REG_SET_ONE(reg,value) ((reg) = ((uint16)value)) 258 259 #endif // __HW_USB_H__ 260