1 #ifndef __PLAT_INTERRUPT_H__
2 #define __PLAT_INTERRUPT_H__
3 
4 #include "rthw.h"
5 #include <rtconfig.h>
6 
7 #if defined(BSP_USING_MMU)
8     #include "mmu.h"
9     #define NONCACHEABLE BIT31
10 #else
11     #define NONCACHEABLE 0
12 #endif
13 
14 #define sysprintf rt_kprintf
15 
16 typedef enum
17 {
18     SYS_IPRST_NA = -1,
19 
20     /* SYS_AHBIPRST, SYS_BA + 0x060 */
21     CHIPRST,
22     AHBIPRST_Reserved_1,
23     CPURST,
24     GDMARST,
25     AHBIPRST_Reserved_4,
26     AHBIPRST_Reserved_5,
27     AHBIPRST_Reserved_6,
28     AHBIPRST_Reserved_7,
29 
30     I2SRST,
31     LCDRST,
32     CAPRST,
33     AHBIPRST_Reserved_11,
34     AHBIPRST_Reserved_12,
35     AHBIPRST_Reserved_13,
36     AHBIPRST_Reserved_14,
37     AHBIPRST_Reserved_15,
38 
39     EMAC0RST,
40     EMAC1RST,
41     USBHRST,
42     USBDRST,
43     FMIRST,
44     GE2DRST,
45     JPEGRST,
46     CRYPTORST,
47 
48     SDIORST,
49     AHBIPRST_Reserved_25,
50     AHBIPRST_Reserved_26,
51     AHBIPRST_Reserved_27,
52     AHBIPRST_Reserved_28,
53     AHBIPRST_Reserved_29,
54     AHBIPRST_Reserved_30,
55     AHBIPRST_Reserved_31,
56 
57     /* SYS_APBIPRST0, SYS_BA + 0x064 */
58     APBIPRST0_Reserved_0,
59     APBIPRST0_Reserved_1,
60     APBIPRST0_Reserved_2,
61     GPIORST,
62     ETIMER0RST,
63     ETIMER1RST,
64     ETIMER2RST,
65     ETIMER3RST,
66 
67     TIMER0RST,
68     TIMER1RST,
69     TIMER2RST,
70     TIMER3RST,
71     TIMER4RST,
72     APBIPRST0_Reserved_13,
73     APBIPRST0_Reserved_14,
74     APBIPRST0_Reserved_15,
75 
76     UART0RST,
77     UART1RST,
78     UART2RST,
79     UART3RST,
80     UART4RST,
81     UART5RST,
82     UART6RST,
83     UART7RST,
84 
85     UART8RST,
86     UART9RST,
87     UART10RST,
88     APBIPRST0_Reserved_27,
89     APBIPRST0_Reserved_28,
90     APBIPRST0_Reserved_29,
91     APBIPRST0_Reserved_30,
92     APBIPRST0_Reserved_31,
93 
94     /* SYS_APBIPRST1, SYS_BA + 0x068 */
95     I2C0RST,
96     I2C1RST,
97     APBIPRST1_Reserved_2,
98     APBIPRST1_Reserved_3,
99     SPI0RST,
100     SPI1RST,
101     APBIPRST1_Reserved_6,
102     APBIPRST1_Reserved_7,
103 
104     CAN0RST,
105     CAN1RST,
106     APBIPRST1_Reserved_10,
107     APBIPRST1_Reserved_11,
108     SMC0RST,
109     SMC1RST,
110     APBIPRST1_Reserved_14,
111     APBIPRST1_Reserved_15,
112 
113     APBIPRST1_Reserved_16,
114     APBIPRST1_Reserved_17,
115     APBIPRST1_Reserved_18,
116     APBIPRST1_Reserved_19,
117     APBIPRST1_Reserved_20,
118     APBIPRST1_Reserved_21,
119     APBIPRST1_Reserved_22,
120     APBIPRST1_Reserved_23,
121 
122     ADCRST,
123     APBIPRST1_Reserved_25,
124     MTPCRST,
125     PWMRST,
126     APBIPRST1_Reserved_28,
127     APBIPRST1_Reserved_29,
128     APBIPRST1_Reserved_30,
129     APBIPRST1_Reserved_31,
130 
131     SYS_IPRST_CNT
132 
133 } E_SYS_IPRST;
134 
135 typedef enum
136 {
137     SYS_IPCLK_NA = -1,
138 
139     /* CLK_HCLKEN, CLK_BA + 0x010 */
140     CPUCKEN,
141     HCLKCKEN,
142     HCLK1CKEN,
143     HCLK3CKEN,
144     HCLK4CKEN,
145     PCLKCKEN,
146     HCLKEN_Reserved_6,
147     TICCKEN,
148 
149     SRAMCKEN,
150     EBICKEN,
151     DDRCKEN,
152     HCLKEN_Reserved_11,
153     GDMACKEN,
154     HCLKEN_Reserved_13,
155     HCLKEN_Reserved_14,
156     CKOCKEN,
157 
158     EMAC0CKEN,
159     EMAC1CKEN,
160     USBHCKEN,
161     USBDCKEN,
162     FMICKEN,
163     NANDCKEN,
164     EMMCCKEN,
165     CRYPTOCKEN,
166 
167     I2SCKEN,
168     LCDCKEN,
169     CAPCKEN,
170     SENSORCKEN,
171     GE2DCKEN,
172     JPEGCKEN,
173     SDHCKEN,
174     HCLKEN_Reserved_31,
175 
176     CLK_HCLKEN_END,
177 
178     /* CLK_BA+0x014 */
179 
180     /* CLK_PCLKEN0 CLK_BA+0x018 */
181     CLK_PCLKEN0_BEGIN = CLK_HCLKEN_END + 32,
182 
183     WDTCKEN = CLK_PCLKEN0_BEGIN,
184     WWDTCKEN,
185     RTCCKEN,
186     GPIOCKEN,
187     ETIMER0CKEN,
188     ETIMER1CKEN,
189     ETIMER2CKEN,
190     ETIMER3CKEN,
191 
192     TIMER0CKEN,
193     TIMER1CKEN,
194     TIMER2CKEN,
195     TIMER3CKEN,
196     TIMER4CKEN,
197     PCLKEN0_Reserved_14,
198     PCLKEN0_Reserved_15,
199     PCLKEN0_Reserved_16,
200 
201     UART0CKEN,
202     UART1CKEN,
203     UART2CKEN,
204     UART3CKEN,
205     UART4CKEN,
206     UART5CKEN,
207     UART6CKEN,
208     UART7CKEN,
209 
210     UART8CKEN,
211     UART9CKEN,
212     UART10CKEN,
213     PCLKEN0_Reserved_27,
214     PCLKEN0_Reserved_28,
215     PCLKEN0_Reserved_29,
216     PCLKEN0_Reserved_30,
217     PCLKEN0_Reserved_31,
218 
219     /* CLK_PCLKEN1, CLK_BA + 0x01C */
220     I2C0CKEN,
221     I2C1CKEN,
222     PCLKEN1_Reserved_2,
223     PCLKEN1_Reserved_3,
224     SPI0CKEN,
225     SPI1CKEN,
226     PCLKEN1_Reserved_6,
227     PCLKEN1_Reserved_7,
228 
229     CAN0CKEN,
230     CAN1CKEN,
231     PCLKEN1_Reserved_10,
232     PCLKEN1_Reserved_11,
233     SMC0CKEN,
234     SMC1CKEN,
235     PCLKEN1_Reserved_14,
236     PCLKEN1_Reserved_15,
237 
238     PCLKEN1_Reserved_16,
239     PCLKEN1_Reserved_17,
240     PCLKEN1_Reserved_18,
241     PCLKEN1_Reserved_19,
242     PCLKEN1_Reserved_20,
243     PCLKEN1_Reserved_21,
244     PCLKEN1_Reserved_22,
245     PCLKEN1_Reserved_23,
246 
247     ADCCKEN,
248     PCLKEN1_Reserved_25,
249     MTPCCKEN,
250     PWMCKEN,
251     PCLKEN1_Reserved_28,
252     PCLKEN1_Reserved_29,
253     PCLKEN1_Reserved_30,
254     PCLKEN1_Reserved_31,
255 
256     SYS_IPCLK_CNT
257 
258 } E_SYS_IPCLK;
259 
260 typedef enum
261 {
262     USB0_ID_DEVICE,
263     USB0_ID_HOST,
264     USB0_ID_CNT
265 } E_SYS_USB0_ID;
266 
267 void rt_hw_interrupt_init(void);
268 void rt_hw_interrupt_set_priority(int vector, int priority);
269 void rt_hw_interrupt_set_type(int vector, int type);
270 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name);
271 
272 void rt_hw_systick_init(void);
273 void nu_clock_base_init(void);
274 
275 void nu_systick_udelay(uint32_t delay_us);
276 void nu_sys_ip_reset(E_SYS_IPRST eIPRstIdx);
277 void nu_sys_ipclk_enable(E_SYS_IPCLK eIPClkIdx);
278 void nu_sys_ipclk_disable(E_SYS_IPCLK eIPClkIdx);
279 E_SYS_USB0_ID nu_sys_usb0_role(void);
280 
281 #endif
282