1 /* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. */ 2 /* 3 * Copyright (C) 2019 ETH Zurich, University of Bologna 4 * and GreenWaves Technologies 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef HAL_INCLUDE_HAL_UART_PERIPH_H_ 20 #define HAL_INCLUDE_HAL_UART_PERIPH_H_ 21 #include "hal_udma_core_periph.h" 22 23 /* ---------------------------------------------------------------------------- 24 -- UART Peripheral Access Layer -- 25 ---------------------------------------------------------------------------- */ 26 27 /** UART_Type Register Layout Typedef */ 28 typedef struct 29 { 30 udma_channel_t rx; /**< UDMA RX channels struct. */ 31 udma_channel_t tx; /**< UDMA TX channels struct. */ 32 volatile uint32_t status; /**< Status register */ 33 volatile uint32_t setup; /**< Configuration register */ 34 } uart_t; 35 36 37 /* ---------------------------------------------------------------------------- 38 -- UART Register Bitfield Access -- 39 ---------------------------------------------------------------------------- */ 40 41 /*! @name STATUS */ 42 /* TX busy status flag */ 43 #define UART_STATUS_TX_BUSY_MASK (0x1) 44 #define UART_STATUS_TX_BUSY_SHIFT (0) 45 #define UART_STATUS_TX_BUSY(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_TX_BUSY_SHIFT)) & UART_STATUS_TX_BUSY_MASK) 46 47 /* RX busy status flag */ 48 #define UART_STATUS_RX_BUSY_MASK (0x2) 49 #define UART_STATUS_RX_BUSY_SHIFT (1) 50 #define UART_STATUS_RX_BUSY(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_BUSY_SHIFT)) & UART_STATUS_RX_BUSY_MASK) 51 52 /* RX parity error status flag */ 53 #define UART_STATUS_RX_PE_MASK (0x4) 54 #define UART_STATUS_RX_PE_SHIFT (2) 55 #define UART_STATUS_RX_PE(val) (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_PE_SHIFT)) & UART_STATUS_RX_PE_MASK) 56 57 58 /*! @name SETUP */ 59 /* Set parity generation and check: 60 - 1'b0: disable 61 - 1'b1: enable */ 62 #define UART_SETUP_PARITY_ENA_MASK (0x1) 63 #define UART_SETUP_PARITY_ENA_SHIFT (0) 64 #define UART_SETUP_PARITY_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_PARITY_ENA_SHIFT)) & UART_SETUP_PARITY_ENA_MASK) 65 66 /* Set character length: 67 - 2'b00: 5 bits 68 - 2'b01: 6 bits 69 - 2'b10: 7 bits 70 - 2'b11: 8 bits */ 71 #define UART_SETUP_BIT_LENGTH_MASK (0x6) 72 #define UART_SETUP_BIT_LENGTH_SHIFT (1) 73 #define UART_SETUP_BIT_LENGTH(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_BIT_LENGTH_SHIFT)) & UART_SETUP_BIT_LENGTH_MASK) 74 75 /* Set stop bits length: 76 - 2'b0: 1 stop bit 77 - 2'b1: 2 stop bits */ 78 #define UART_SETUP_STOP_BITS_MASK (0x8) 79 #define UART_SETUP_STOP_BITS_SHIFT (3) 80 #define UART_SETUP_STOP_BITS(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_STOP_BITS_SHIFT)) & UART_SETUP_STOP_BITS_MASK) 81 82 /* Set TX transceiver state: 83 - 1'b0: disable 84 - 1'b1: enable */ 85 #define UART_SETUP_TX_ENA_MASK (0x100) 86 #define UART_SETUP_TX_ENA_SHIFT (8) 87 #define UART_SETUP_TX_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_TX_ENA_SHIFT)) & UART_SETUP_TX_ENA_MASK) 88 89 /* Set RX transceiver state: 90 - 1'b0: disable 91 - 1'b1: enable */ 92 #define UART_SETUP_RX_ENA_MASK (0x200) 93 #define UART_SETUP_RX_ENA_SHIFT (9) 94 #define UART_SETUP_RX_ENA(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_RX_ENA_SHIFT)) & UART_SETUP_RX_ENA_MASK) 95 96 /* Sets the clock divider ratio for the baud rate generator. */ 97 #define UART_SETUP_CLKDIV_MASK (0xffff0000) 98 #define UART_SETUP_CLKDIV_SHIFT (16) 99 #define UART_SETUP_CLKDIV(val) (((uint32_t)(((uint32_t)(val)) << UART_SETUP_CLKDIV_SHIFT)) & UART_SETUP_CLKDIV_MASK) 100 101 102 /*! @name STATUS */ 103 typedef union 104 { 105 struct 106 { 107 /* TX busy status flag */ 108 uint32_t tx_busy:1; 109 /* RX busy status flag */ 110 uint32_t rx_busy:1; 111 /* RX parity error status flag */ 112 uint32_t rx_pe:1; 113 } field; 114 uint32_t word; 115 } uart_status_t; 116 117 /*! @name SETUP */ 118 typedef union 119 { 120 struct 121 { 122 /* Set parity generation and check: 123 - 1'b0: disable 124 - 1'b1: enable */ 125 uint32_t parity_ena:1; 126 /* Set character length: 127 - 2'b00: 5 bits 128 - 2'b01: 6 bits 129 - 2'b10: 7 bits 130 - 2'b11: 8 bits */ 131 uint32_t bit_length:2; 132 /* Set stop bits length: 133 - 2'b0: 1 stop bit 134 - 2'b1: 2 stop bits */ 135 uint32_t stop_bits:1; 136 uint32_t reserved_0:4; 137 /* Set TX transceiver state: 138 - 1'b0: disable 139 - 1'b1: enable */ 140 uint32_t tx_ena:1; 141 /* Set RX transceiver state: 142 - 1'b0: disable 143 - 1'b1: enable */ 144 uint32_t rx_ena:1; 145 uint32_t reserved_1:6; 146 /* Sets the clock divider ratio for the baud rate generator. */ 147 uint32_t clkdiv:16; 148 } field; 149 uint32_t word; 150 } uart_setup_t; 151 152 153 #endif /* HAL_INCLUDE_HAL_UART_PERIPH_H_ */ 154