1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "fsl_pit.h"
32
33 /*******************************************************************************
34 * Prototypes
35 ******************************************************************************/
36 /*!
37 * @brief Gets the instance from the base address to be used to gate or ungate the module clock
38 *
39 * @param base PIT peripheral base address
40 *
41 * @return The PIT instance
42 */
43 static uint32_t PIT_GetInstance(PIT_Type *base);
44
45 /*******************************************************************************
46 * Variables
47 ******************************************************************************/
48 /*! @brief Pointers to PIT bases for each instance. */
49 static PIT_Type *const s_pitBases[] = PIT_BASE_PTRS;
50
51 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
52 /*! @brief Pointers to PIT clocks for each instance. */
53 static const clock_ip_name_t s_pitClocks[] = PIT_CLOCKS;
54 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
55
56 /*******************************************************************************
57 * Code
58 ******************************************************************************/
PIT_GetInstance(PIT_Type * base)59 static uint32_t PIT_GetInstance(PIT_Type *base)
60 {
61 uint32_t instance;
62
63 /* Find the instance index from base address mappings. */
64 for (instance = 0; instance < ARRAY_SIZE(s_pitBases); instance++)
65 {
66 if (s_pitBases[instance] == base)
67 {
68 break;
69 }
70 }
71
72 assert(instance < ARRAY_SIZE(s_pitBases));
73
74 return instance;
75 }
76
PIT_Init(PIT_Type * base,const pit_config_t * config)77 void PIT_Init(PIT_Type *base, const pit_config_t *config)
78 {
79 assert(config);
80
81 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
82 /* Ungate the PIT clock*/
83 CLOCK_EnableClock(s_pitClocks[PIT_GetInstance(base)]);
84 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
85
86 /* Enable PIT timers */
87 base->MCR &= ~PIT_MCR_MDIS_MASK;
88
89 /* Config timer operation when in debug mode */
90 if (config->enableRunInDebug)
91 {
92 base->MCR &= ~PIT_MCR_FRZ_MASK;
93 }
94 else
95 {
96 base->MCR |= PIT_MCR_FRZ_MASK;
97 }
98 }
99
PIT_Deinit(PIT_Type * base)100 void PIT_Deinit(PIT_Type *base)
101 {
102 /* Disable PIT timers */
103 base->MCR |= PIT_MCR_MDIS_MASK;
104
105 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
106 /* Gate the PIT clock*/
107 CLOCK_DisableClock(s_pitClocks[PIT_GetInstance(base)]);
108 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
109 }
110
111 #if defined(FSL_FEATURE_PIT_HAS_LIFETIME_TIMER) && FSL_FEATURE_PIT_HAS_LIFETIME_TIMER
112
PIT_GetLifetimeTimerCount(PIT_Type * base)113 uint64_t PIT_GetLifetimeTimerCount(PIT_Type *base)
114 {
115 uint32_t valueH = 0U;
116 uint32_t valueL = 0U;
117
118 /* LTMR64H should be read before LTMR64L */
119 valueH = base->LTMR64H;
120 valueL = base->LTMR64L;
121
122 return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
123 }
124
125 #endif /* FSL_FEATURE_PIT_HAS_LIFETIME_TIMER */
126