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Searched refs:BaseAddress (Results 1 – 25 of 86) sorted by relevance

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/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/gpiops_v3_7/
A Dxgpiops_hw.c62 void XGpioPs_ResetHw(u32 BaseAddress) in XGpioPs_ResetHw() argument
91 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
94 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
101 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
121 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
152 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
156 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
160 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
215 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
219 XGpioPs_WriteReg(BaseAddress, in XGpioPs_ResetHw()
[all …]
/bsp/ft2004/libraries/bsp/ft_gmac/
A Dft_gmac_hw.c35 TmpReg = Ft_in32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET); in Gmac_WritePHYRegister()
44 Ft_out32(Config->BaseAddress + GMAC_MII_ADDR_OFFSET, TmpReg); in Gmac_WritePHYRegister()
208 Ft_out32(Config->BaseAddress + GMAC_HASH_HIGH_OFFSET, 0); in FGmac_MACDMAInit()
210 Ft_out32(Config->BaseAddress + GMAC_HASH_LOW_OFFSET, 0); in FGmac_MACDMAInit()
246 RegValue = Ft_in32(Config->BaseAddress + DMA_OP_OFFSET); in FGmac_MACDMAInit()
254 Ft_out32(Config->BaseAddress + DMA_OP_OFFSET, RegValue); in FGmac_MACDMAInit()
300 …Ft_out32(Config->BaseAddress + DMA_OP_OFFSET, Ft_in32(Config->BaseAddress + DMA_OP_OFFSET) | DMA_O… in FGmac_InitializeHw()
321 Ft_out32(Config->BaseAddress + DMA_INTR_ENA_OFFSET, 0); in FGmac_InitializeHw()
487 RegValue = Ft_in32(Config->BaseAddress + DMA_OP_OFFSET); in FGmac_FlushTransmitFIFO()
489 Ft_out32(Config->BaseAddress + DMA_OP_OFFSET, RegValue); in FGmac_FlushTransmitFIFO()
[all …]
A Dft_gmac_intr.c67 RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET); in FGmac_ErrorCheck()
68 ErrIsr_RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_INTR_ENA_OFFSET); in FGmac_ErrorCheck()
137 RegValue = Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET); in FGmac_IntrHandler()
140 MACRegValue = Ft_in32(Gmac->Config.BaseAddress + GMAC_MAC_MAC_PHY_STATUS); in FGmac_IntrHandler()
155 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_RI); in FGmac_IntrHandler()
160 …Ft_printf("ti debug %x \r\n", Ft_in32(Gmac->Config.BaseAddress + GMAC_INTERNAL_MODULE_STATUS_OFFSE… in FGmac_IntrHandler()
162 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_TI); in FGmac_IntrHandler()
165 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_NIS); in FGmac_IntrHandler()
168 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_AIS) == DMA_STATUS_AIS) in FGmac_IntrHandler()
172 …Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, Ft_in32(Gmac->Config.BaseAddress + DMA_STAT… in FGmac_IntrHandler()
A Dft_gmac_desc.c35 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_TU) == DMA_STATUS_TU) in FGmac_ResumeTransmission()
38 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_TU); in FGmac_ResumeTransmission()
41 Ft_out32(Gmac->Config.BaseAddress + DMA_XMT_POLL_DEMAND_OFFSET, 0xff); in FGmac_ResumeTransmission()
48 if ((Ft_in32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET) & DMA_STATUS_UNF) == DMA_STATUS_UNF) in FGmac_SetTransmitUnderflow()
51 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_UNF); in FGmac_SetTransmitUnderflow()
54 Ft_out32(Gmac->Config.BaseAddress + DMA_XMT_POLL_DEMAND_OFFSET, 0xff); in FGmac_SetTransmitUnderflow()
108 Ft_out32(Gmac->Config.BaseAddress + DMA_TX_BASE_ADDR_OFFSET, (u32)DMATxDescTab); in FGmac_DmaTxDescRingInit()
223 Ft_out32(Gmac->Config.BaseAddress + DMA_RCV_BASE_ADDR_OFFSET, (u32)DMARxDescTab); in FGmac_DMARxDescChainInit()
255 Ft_out32(Gmac->Config.BaseAddress + DMA_RCV_BASE_ADDR_OFFSET, (u32)DMARxDescTab); in FGmac_DmaRxDescRingInit()
266 Ft_out32(Gmac->Config.BaseAddress + DMA_STATUS_OFFSET, DMA_STATUS_RU); in FGmac_ResumeTransmissionReception()
[all …]
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/emacps_v3_11/
A Dxemacps.c89 InstancePtr->Config.BaseAddress = EffectiveAddress; in XEmacPs_CfgInitialize()
156 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Start()
160 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Start()
244 Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_Stop()
248 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Stop()
316 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
330 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
338 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
358 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
366 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_Reset()
[all …]
A Dxemacps_control.c89 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMacAddress()
102 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMacAddress()
244 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetHash()
250 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetHash()
338 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_ClearHash()
342 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_ClearHash()
404 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetTypeIdCheck()
795 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SendPausePacket()
928 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_SetMdioDivisor()
993 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_PhyRead()
[all …]
A Dxemacps_intr.c138 RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
155 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
167 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
170 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
181 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
191 RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
193 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
201 XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
204 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
223 XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, in XEmacPs_IntrHandler()
[all …]
A Dxemacps.h511 UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ member
601 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
622 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
643 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
664 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
683 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
685 (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
707 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
730 ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \
757 XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \
[all …]
/bsp/ft2004/libraries/bsp/ft_uart/
A Dft_uart_hw.c17 void FUart_SendByte(u32 BaseAddress, u8 Byte) in FUart_SendByte() argument
19 while (FT_UART_IsTransmitFull(BaseAddress)) in FUart_SendByte()
23 FT_UART_WriteReg(BaseAddress, UARTDR_OFFSET, (u32)Byte); in FUart_SendByte()
26 u8 FUart_RecvByte(u32 BaseAddress) in FUart_RecvByte() argument
29 while (FT_UART_IsReceiveData(BaseAddress)) in FUart_RecvByte()
33 RecievedByte = FT_UART_ReadReg(BaseAddress, UARTDR_OFFSET); in FUart_RecvByte()
37 u8 FUart_GetChar(u32 BaseAddress) in FUart_GetChar() argument
40 if (FT_UART_IsReceiveData(BaseAddress)) in FUart_GetChar()
44 RecievedByte = FT_UART_ReadReg(BaseAddress, UARTDR_OFFSET); in FUart_GetChar()
A Dft_uart.c43 UartPtr->Config.BaseAddress = Config->BaseAddress; in FUart_CfgInitialize()
68 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTLCR_H_OFFSET, RegValue); in FUart_CfgInitialize()
72 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIFLS_OFFSET, RegValue); in FUart_CfgInitialize()
76 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, RegValue); in FUart_CfgInitialize()
100 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_Send()
102 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, RegValue); in FUart_Send()
125 while (!FT_UART_IsTransmitFull(UartPtr->Config.BaseAddress)) in FUart_PutChar()
127 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTDR_OFFSET, Data); in FUart_PutChar()
197 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, 0); in FUart_Receive()
273 FUart_SendByte(UartPtr->Config.BaseAddress, BytePtr[index]); in FUart_BlockSend()
[all …]
A Dft_uart_hw.h184 #define FT_UART_ReadReg(BaseAddress, RegOffset) Ft_in32(BaseAddress + (u32)RegOffset) argument
194 #define FT_UART_WriteReg(BaseAddress, RegOffset, RegisterValue) Ft_out32(BaseAddress + (u32)RegOffs… argument
203 #define FT_UART_IsReceiveData(BaseAddress) (Ft_in32(BaseAddress + UARTFTR_OFFSET) & UARTFTR_RXFE) argument
211 #define FT_UART_IsTransmitFull(BaseAddress) ((Ft_in32(BaseAddress + UARTFTR_OFFSET) & (u32)UARTFTR_… argument
213 void FUart_SendByte(u32 BaseAddress, u8 Byte);
214 u8 FUart_RecvByte(u32 BaseAddress);
215 u8 FUart_GetChar(u32 BaseAddress);
A Dft_uart_options.c47 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_SetOptions()
58 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_SetOptions()
75 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_SetSpecificOptions()
79 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_SetSpecificOptions()
96 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset); in FUart_ClearSpecificOptions()
100 FT_UART_WriteReg(UartPtr->Config.BaseAddress, OptionTable[Index].RegisterOffset, RegValue); in FUart_ClearSpecificOptions()
A Dft_uart_intr.c35 return FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_GetInterruptMask()
45 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, TempMask); in FUart_SetInterruptMask()
77 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_InterruptHandler()
79 RegValue &= FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTMIS_OFFSET); in FUart_InterruptHandler()
111 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTICR_OFFSET, in FUart_InterruptHandler()
181 RegValue = FT_UART_ReadReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET); in FUart_sendDataHandler()
183 FT_UART_WriteReg(UartPtr->Config.BaseAddress, UARTIMSC_OFFSET, RegValue); in FUart_sendDataHandler()
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/sdps_v3_9/
A Dxsdps_hw.h1164 XSdPs_In32((BaseAddress) + (RegOffset))
1203 BaseAddress += RegOffset & 0xFC; in XSdPs_ReadReg16()
1204 Reg = XSdPs_In32(BaseAddress); in XSdPs_ReadReg16()
1233 BaseAddress += RegOffset & 0xFC; in XSdPs_WriteReg16()
1234 Reg = XSdPs_In32(BaseAddress); in XSdPs_WriteReg16()
1237 XSdPs_Out32(BaseAddress, Reg); in XSdPs_WriteReg16()
1261 BaseAddress += RegOffset & 0xFC; in XSdPs_ReadReg8()
1262 Reg = XSdPs_In32(BaseAddress); in XSdPs_ReadReg8()
1289 BaseAddress += RegOffset & 0xFC; in XSdPs_WriteReg8()
1290 Reg = XSdPs_In32(BaseAddress); in XSdPs_WriteReg8()
[all …]
A Dxsdps_card.c192 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_IdentifyCard()
194 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_IdentifyCard()
743 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_HostConfig()
992 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_Change_SdBusSpeed()
1236 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_DllReset()
1358 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetClock()
1436 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
1439 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
1443 XSdPs_WriteReg(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
1446 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetupCmd()
[all …]
A Dxsdps_host.c118 if(XSdPs_ReadReg(InstancePtr->Config.BaseAddress, in XSdPs_SetupTransfer()
183 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetExecTuning()
725 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_EnableClock()
744 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_EnableClock()
844 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetupReadDma()
887 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_SetupWriteDma()
1372 XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, in XSdPs_ConfigPower()
1415 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_ConfigInterrupt()
1419 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_ConfigInterrupt()
1424 XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, in XSdPs_ConfigInterrupt()
[all …]
/bsp/zynqmp-r5-axu4ev/drivers/Zynq_HAL_Driver/xemacpsif/
A Dxemacpsif_dma.c147 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in get_base_index_txpbufsstorage()
152 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) { in get_base_index_txpbufsstorage()
157 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) { in get_base_index_txpbufsstorage()
162 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) { in get_base_index_txpbufsstorage()
174 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in get_base_index_rxpbufsstorage()
179 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_1_BASEADDR) { in get_base_index_rxpbufsstorage()
184 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_2_BASEADDR) { in get_base_index_rxpbufsstorage()
189 if (xemacpsif->emacps.Config.BaseAddress == XPAR_XEMACPS_3_BASEADDR) { in get_base_index_rxpbufsstorage()
362 XEmacPs_WriteReg((xemacpsif->emacps).Config.BaseAddress, in emacps_sgsend()
364 (XEmacPs_ReadReg((xemacpsif->emacps).Config.BaseAddress, in emacps_sgsend()
[all …]
A Dxemacpsif_hw.c58 if (XEmacPs_ConfigTable[i].BaseAddress == mac_base) { in xemacps_lookup_config()
112 if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in init_emacps()
127 if (xemacpsp->Config.BaseAddress == XPAR_XEMACPS_0_BASEADDR) { in init_emacps()
203 Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
206 XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
209 Reg = XEmacPs_ReadReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
212 XEmacPs_WriteReg(xemacps->emacps.Config.BaseAddress, in restart_emacps_transmitter()
A Dxemacpsif.c361 if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) { in low_level_init()
364 if (mac_config->BaseAddress == VERSAL_EMACPS_0_BASEADDR) { in low_level_init()
370 mac_config->BaseAddress); in low_level_init()
378 dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, in low_level_init()
381 XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, in low_level_init()
419 mac_config->BaseAddress); in HandleEmacPsError()
425 dmacrreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, in HandleEmacPsError()
428 XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, in HandleEmacPsError()
445 netctrlreg = XEmacPs_ReadReg(xemacpsif->emacps.Config.BaseAddress, in HandleTxErrors()
448 XEmacPs_WriteReg(xemacpsif->emacps.Config.BaseAddress, in HandleTxErrors()
[all …]
/bsp/ft2004/libraries/bsp/ft_i2c/
A Dft_i2c.c105 pCfg->BaseAddress = g_FI2cRegBaseAddr[id]; in FI2C_initMasterCfg()
174 FI2C_resetReg(pDev->Config.BaseAddress); in FI2C_initMaster()
177 FI2C_setSclClk(pDev->Config.BaseAddress, in FI2C_initMaster()
183 FI2C_setCtrlParam(pDev->Config.BaseAddress, in FI2C_initMaster()
284 FI2C_sendRestartCmd(pDev->Config.BaseAddress); in FI2C_writeByByte()
288 FI2C_sendWriteCmd(pDev->Config.BaseAddress, PageAddr); in FI2C_writeByByte()
352 FI2C_sendRestartCmd(pDev->Config.BaseAddress); in FI2C_readByByte()
358 FI2C_sendStartReadCmd(pDev->Config.BaseAddress, PageAddr); in FI2C_readByByte()
429 FI2C_sendRestartCmd(pDev->Config.BaseAddress); in FI2C_writeByFifo()
433 FI2C_sendWriteCmd(pDev->Config.BaseAddress, PageAddr); in FI2C_writeByFifo()
[all …]
/bsp/zynqmp-r5-axu4ev/drivers/
A Ddrv_sdcard.c56 static u32 BaseAddress; variable
77 if (SdInstance[pdrv].Config.BaseAddress == (u32)0) in disk_status()
82 BaseAddress = XPAR_XSDPS_1_BASEADDR; in disk_status()
89 BaseAddress = XPAR_XSDPS_0_BASEADDR; in disk_status()
95 HostCntrlrVer[pdrv] = (u8)(XSdPs_ReadReg16(BaseAddress, in disk_status()
100 SlotType[pdrv] = XSdPs_ReadReg(BaseAddress, in disk_status()
111 if ((XSdPs_ReadReg8((u32)BaseAddress, XSDPS_POWER_CTRL_OFFSET) & in disk_status()
117 StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress); in disk_status()
134 StatusReg = XSdPs_GetPresentStatusReg((u32)BaseAddress); in disk_status()
193 (XSdPs_GetPresentStatusReg((u32)BaseAddress) & in disk_initialize()
[all …]
A Ddrv_uart.h255 #define UartDataReceived(BaseAddress) \ argument
256 !((__REG32((BaseAddress) + UART_SR_OFFSET) & \
272 #define UartTXFIFOFull(BaseAddress) \ argument
273 ((__REG32((BaseAddress) + UART_SR_OFFSET) & \
/bsp/stm32/stm32h750-artpi/board/port/
A Ddrv_mpu.c22 MPU_InitStruct.BaseAddress = 0x24000000; in mpu_init()
38 MPU_InitStruct.BaseAddress = 0xC0000000; in mpu_init()
56 MPU_InitStruct.BaseAddress = 0x30040000; in mpu_init()
72 MPU_InitStruct.BaseAddress = 0x90000000; in mpu_init()
/bsp/stm32/stm32h730-esphosted-evb/board/
A Dboard.c78 MPU_InitStruct.BaseAddress = 0x00000000; in MPU_Config()
91 MPU_InitStruct.BaseAddress = 0x20000000; in MPU_Config()
104 MPU_InitStruct.BaseAddress = 0x24000000; in MPU_Config()
117 MPU_InitStruct.BaseAddress = 0x30000000; in MPU_Config()
130 MPU_InitStruct.BaseAddress = 0x38000000; in MPU_Config()
143 MPU_InitStruct.BaseAddress = 0x90000000; in MPU_Config()
/bsp/microblaze/
A Dboard.c161 csr = XTmrCtr_ReadReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET); in rt_hw_timer_handler()
168 …XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, csr | XTC_CSR_INT_OCCURED_MASK); in rt_hw_timer_handler()
210 XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TLR_OFFSET, PIV); in rt_tmr_init()
212 XTmrCtr_WriteReg(timer.BaseAddress, TIMER_CNTR_0, XTC_TCSR_OFFSET, ctl); in rt_tmr_init()

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