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Searched refs:CCU_REG_BASE (Results 1 – 3 of 3) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw19p1/
A Dclk_sun8iw19.h50 #define CCU_REG_BASE (0x03001000) macro
51 #define CLK_PLL_CPU (volatile uint32_t *)(CCU_REG_BASE + 0x0000)
52 #define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010)
53 #define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020)
54 #define CLK_PLL_PERIPH1 (volatile uint32_t *)(CCU_REG_BASE + 0x0028)
55 #define CLK_PLL_VIDEO0 (volatile uint32_t *)(CCU_REG_BASE + 0x0040)
56 #define CLK_PLL_AUDIO (volatile uint32_t *)(CCU_REG_BASE + 0x0078)
57 #define CLK_PLL_CSI (volatile uint32_t *)(CCU_REG_BASE + 0x00E0)
60 #define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110)
61 #define CLK_PLL_PERI0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0120)
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/bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/sun8iw18p1/
A Dclk_sun8iw18.h50 #define CCU_REG_BASE (0x03001000) macro
51 #define CLK_PLL_CPU (volatile uint32_t *)(CCU_REG_BASE + 0x0000)
52 #define CLK_PLL_DDR (volatile uint32_t *)(CCU_REG_BASE + 0x0010)
53 #define CLK_PLL_PERIPH0 (volatile uint32_t *)(CCU_REG_BASE + 0x0020)
54 #define CLK_PLL_PERIPH1 (volatile uint32_t *)(CCU_REG_BASE + 0x0028)
55 #define CLK_PLL_AUDIO (volatile uint32_t *)(CCU_REG_BASE + 0x0078)
56 #define CLK_PLL_32K (volatile uint32_t *)(CCU_REG_BASE + 0x00d8)
59 #define CLK_PLL_DDRPAT (volatile uint32_t *)(CCU_REG_BASE + 0x0110)
60 #define CLK_PLL_PERI0PAT0 (volatile uint32_t *)(CCU_REG_BASE + 0x0120)
61 #define CLK_PLL_PERI0PAT1 (volatile uint32_t *)(CCU_REG_BASE + 0x0124)
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/bsp/allwinner/libraries/sunxi-hal/hal/source/prcm/prcm-sun50iw11/
A Dccu_i.h27 #define CCU_REG_BASE SUNXI_CCU_REG_PBASE macro
36 #define CCU_PLL_DDR0_REG (CCU_REG_BASE + 0x800)
46 #define CCU_CPU_AXI_CFG_REG (CCU_REG_BASE + 0x500)
47 #define CCU_PSI_AHB1_AHB2_CFG_REG (CCU_REG_BASE + 0x510)
48 #define CCU_APB1_CFG_REG (CCU_REG_BASE + 0x520)
49 #define CCU_APB2_CFG_REG (CCU_REG_BASE + 0x524)
50 #define CCU_CCI_CFG_REG (CCU_REG_BASE + 0x530)
51 #define CCU_MBUS_CLK_REG (CCU_REG_BASE + 0x540)
52 #define CCU_MBUS_MASTER_CLK_REG (CCU_REG_BASE + 0x804)
53 #define CCU_MSGBOX_BGR_REG (CCU_REG_BASE + 0x71c)
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