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Searched refs:DRV_IOREMAP (Results 1 – 18 of 18) sorted by relevance

/bsp/cvitek/drivers/libraries/sdif/
A Ddw_sdmmc.h62 #define SDIO0_BASE DRV_IOREMAP((void *)DW_SDIO1_BASE, 0x1000)
63 #define SDIO1_BASE DRV_IOREMAP((void *)DW_SDIO0_BASE, 0x1000)
64 #define SDIO2_BASE DRV_IOREMAP((void *)DW_SDIO2_BASE, 0x1000)
275 #define RTCIO_BASE (uintptr_t)DRV_IOREMAP((void *)0x5027000, 0x1000)
315 #define RTC_CTRL_BASE (uintptr_t)DRV_IOREMAP((void *)0x5025000, 0x1000)
320 #define RTCSYS_CTRL_BASE (uintptr_t)DRV_IOREMAP((void *)0x03000000, 0x1000)
369 #define CLK_DIV_BASE (uintptr_t)DRV_IOREMAP((void *)0x3002000, 0x1000)
/bsp/cvitek/drivers/
A Ddrv_ioremap.h19 #define DRV_IOREMAP(addr, size) rt_ioremap(addr, size) macro
22 #define DRV_IOREMAP(addr, size) (addr) macro
A Ddrv_por.c57 _cvi_rtc_ctrl_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_ctrl_base, 0x1000); in rt_hw_cpu_reset()
58 _cvi_rtc_reg_base = (rt_ubase_t)DRV_IOREMAP((void *)_cvi_rtc_reg_base, 0x1000); in rt_hw_cpu_reset()
A Ddrv_uart.c453 uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); in rt_hw_uart_init()
461 uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); in rt_hw_uart_init()
469 uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); in rt_hw_uart_init()
477 uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); in rt_hw_uart_init()
485 uart->hw_base = (rt_ubase_t)DRV_IOREMAP((void*)uart->hw_base, 0x10000); in rt_hw_uart_init()
A Ddrv_wdt.c25 rt_ubase_t base = (rt_ubase_t)DRV_IOREMAP((void *)(CV_TOP + CV_TOP_WDT_OFFSET), 0x1000); in cvi_wdt_top_setting()
29 base = (rt_ubase_t)DRV_IOREMAP((void *)CV_RST_REG, 0x1000); in cvi_wdt_top_setting()
233 _wdt_dev[i].base = (rt_ubase_t)DRV_IOREMAP((void *)_wdt_dev[i].base, 0x1000); in rt_hw_wdt_init()
A Ddrv_eth.h18 #define DW_MAC_BASE DRV_IOREMAP((void *)0x04070000, 0x10000)
A Ddrv_adc.c255 adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(SARADC_BASE, 0x10000); in rt_hw_adc_init()
259 adc_dev_config[i].base = (rt_ubase_t)DRV_IOREMAP(RTC_ADC_BASE, 0x1000); in rt_hw_adc_init()
A Ddrv_rtc.c96 rt_ubase_t clk = (rt_ubase_t)DRV_IOREMAP((void *)CLK_EN_0, 0x1000); in hal_cvi_rtc_clk_set()
394 rtc_device.base = (rt_ubase_t)DRV_IOREMAP((void *)rtc_device.base, 0x1000); in rt_hw_rtc_init()
A Ddrv_gpio.c304 dwapb_gpio_base = (rt_ubase_t)DRV_IOREMAP((void *)dwapb_gpio_base, 0x1000); in rt_hw_gpio_init()
305 dwapb_gpio_base_e = (rt_ubase_t)DRV_IOREMAP((void *)dwapb_gpio_base_e, 0x1000); in rt_hw_gpio_init()
A Ddrv_pwm.c330 cvi_pwm[i].device.base = (rt_ubase_t)DRV_IOREMAP((void *)cvi_pwm[i].device.base, 0x1000); in rt_hw_pwm_init()
A Ddrv_spi.c338 _spi_obj[i].dws.regs = (void *)DRV_IOREMAP((void *)_spi_obj[i].dws.regs, 0x1000); in rt_hw_spi_init()
A Ddrv_timer.c427 _timer_obj[i].base = (dw_timer_regs_t *)DRV_IOREMAP((void*)_timer_obj[i].base, 0x10000); in rt_hw_timer_init()
A Ddrv_hw_i2c.c587 _i2c_obj->iic_base = (rt_ubase_t)DRV_IOREMAP((void *)_i2c_obj->iic_basee, 0x10000); in rt_hw_i2c_init()
/bsp/cvitek/drivers/libraries/eth/
A Deth_phy_cvitek.c31 #define CVITEK_EFUSE_BASE (uintptr_t)DRV_IOREMAP((void *)0x03050000, 0x2000)
253 uintptr_t addr = (uintptr_t)DRV_IOREMAP((void *)0x03001000, 0x1000); in cv181x_config()
258 addr = (uintptr_t)DRV_IOREMAP((void *)0x05027000, 0x1000); in cv181x_config()
A Dcvi_eth_phy.h352 #define ETH_PHY_BASE (uintptr_t)DRV_IOREMAP((void *)0x03009000, 0x1000)
A Ddw_eth_mac.c348 uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000); in designware_eth_send()
425 uint64_t data_start = (uint64_t)DRV_IOREMAP((void *)desc_p->dmamac_addr, 0x1000); in designware_eth_recv()
/bsp/cvitek/drivers/libraries/cv181x/
A Dpinctrl.h26 #define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000)
/bsp/cvitek/drivers/libraries/cv180x/
A Dpinctrl.h26 #define PINMUX_BASE (uintptr_t)DRV_IOREMAP((void *)0x3001000, 0x1000)

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