FSL_FEATURE_MCG_PLL_PRDIV_BASE (reference) in projects: bsp

Searched refs:FSL_FEATURE_MCG_PLL_PRDIV_BASE (Results 1 – 2 of 2) sorted by relevance

/bsp/frdm-k64f/device/MK64F12/
A D	fsl_clock.c	`646 mcgpll0clk /= (FSL_FEATURE_MCG_PLL_PRDIV_BASE + MCG_C5_PRDIV0_VAL); in CLOCK_GetPll0Freq() 764 … (FSL_FEATURE_MCG_PLL_REF_MAX * (FSL_FEATURE_MCG_PLL_PRDIV_MAX + FSL_FEATURE_MCG_PLL_PRDIV_BASE)))) in CLOCK_CalcPllDiv() 793 prdiv = prdiv_cur - FSL_FEATURE_MCG_PLL_PRDIV_BASE; in CLOCK_CalcPllDiv() 822 prdiv = ret_prdiv - FSL_FEATURE_MCG_PLL_PRDIV_BASE; in CLOCK_CalcPllDiv()`
/bsp/frdm-k64f/device/
A D	MK64F12_features.h	`1445 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) macro`

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