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Searched refs:HALF (Results 1 – 9 of 9) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/phy/
A Dhal_miiphyutil.c541 return HALF; in miiphy_duplex()
559 FULL : HALF; in miiphy_duplex()
562 return (bmcr & BMCR_FULLDPLX) ? FULL : HALF; in miiphy_duplex()
566 return HALF; in miiphy_duplex()
/bsp/allwinner/libraries/sunxi-hal/include/hal/phy/
A Dsunxi_hal_miiphy.h116 #define HALF 22 macro
/bsp/renesas/ra6m3-hmi-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA6M3AH.h1808 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra8d1-vision-board/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h2186 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra8d1-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A DR7FA8D1BH.h2186 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra2l1-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2345 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra6m4-cpk/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2345 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra6m4-iot/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2345 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member
/bsp/renesas/ra6m3-ek/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/
A Drenesas.h2345 … __IOM uint32_t HALF : 11; /*!< [26..16] Vertical synchronization signal generation change timing member

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