Searched refs:L1C_BASE (Results 1 – 14 of 14) sorted by relevance
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/ |
| A D | bl702_l1c.c | 106 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_Cache_Enable_Set()
112 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
116 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
123 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
139 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
146 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
161 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
164 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
168 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
176 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Cache_Enable_Set()
[all …]
|
| A D | bl702_common.c | 104 if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { in ASM_Delay_Us()
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/ |
| A D | bl602_l1c.c | 105 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_Set_Wrap()
113 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_Set_Wrap()
121 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Set_Wrap()
147 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_Set_Way_Disable()
155 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_Set_Way_Disable()
157 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_Set_Way_Disable()
182 tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); in L1C_IROM_2T_Access_Set()
190 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_IROM_2T_Access_Set()
214 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_BMX_Init()
276 BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); in L1C_BMX_BusErrResponse_Enable()
[all …]
|
| A D | bl602_common.c | 69 if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) { in ASM_Delay_Us()
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/ |
| A D | bl602_l1c.h | 146 #define L1C_CONF_REG_NP (L1C_BASE + 0x00)
147 #define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE + 0x04)
148 #define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE + 0x08)
149 #define L1C_MISS_CNT_REG_NP (L1C_BASE + 0x0C)
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/ |
| A D | bl702_l1c.h | 152 #define L1C_CONF_REG (L1C_BASE + 0x00)
153 #define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04)
154 #define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08)
155 #define L1C_MISS_CNT_REG (L1C_BASE + 0x0C)
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/ |
| A D | bl602_memorymap.h | 50 #define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/ |
| A D | bl702_memorymap.h | 61 #define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/ |
| A D | bl616_memorymap.h | 72 #define L1C_BASE ((uint32_t)0x20009000) macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/ |
| A D | bl808_memorymap.h | 75 #define L1C_BASE ((uint32_t)0x20009000) macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ |
| A D | bl602.h | 161 #define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ |
| A D | bl702.h | 182 #define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */ macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ |
| A D | bl616.h | 206 #define L1C_BASE ((uint32_t)0x20009000) macro
|
| /bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ |
| A D | bl808.h | 419 #define L1C_BASE ((uint32_t)0x20009000) macro
|
Completed in 29 milliseconds