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Searched refs:MBUS_MAT_CLK_GATING_REG (Results 1 – 5 of 5) sorted by relevance

/bsp/allwinner/libraries/sunxi-hal/hal/source/ce/platform/
A Dce_sun8iw18.h21 #define MBUS_MAT_CLK_GATING_REG (SUNXI_CCM_BASE + 0x804) macro
A Dce_sun8iw19.h22 #define MBUS_MAT_CLK_GATING_REG (SUNXI_CCM_BASE + 0x804) macro
A Dce_sun20iw1.h25 #define MBUS_MAT_CLK_GATING_REG (SUNXI_CCM_BASE + 0x804) macro
A Dce_sun20iw2.h26 #define MBUS_MAT_CLK_GATING_REG (SUNXI_CCM_BASE + 0x804) macro
/bsp/allwinner/libraries/sunxi-hal/hal/source/ce/
A Dhal_ce.c106 reg_val = readl(MBUS_MAT_CLK_GATING_REG); in hal_ce_clock_init()
108 writel(reg_val, MBUS_MAT_CLK_GATING_REG); in hal_ce_clock_init()

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