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Searched refs:PLLDiv (Results 1 – 3 of 3) sorted by relevance

/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Src/
A Dstm32l1xx_ll_utils.c346 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSI()
424 …L_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLMul, UTILS_PLLInitStruct->PLLDiv); in LL_PLL_ConfigSystemClock_HSE()
463 assert_param(IS_LL_UTILS_PLLDIV_VALUE(UTILS_PLLInitStruct->PLLDiv)); in UTILS_GetPLLOutputFrequency()
475 pllfreq = pllfreq / ((UTILS_PLLInitStruct->PLLDiv >> RCC_CFGR_PLLDIV_Pos)+1U); in UTILS_GetPLLOutputFrequency()
/bsp/stm32/libraries/STM32L1xx_HAL/STM32L1xx_HAL_Driver/Inc/
A Dstm32l1xx_ll_utils.h98 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock. member
A Dstm32l1xx_ll_rcc.h1219 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul, uint32_t PLLDiv) in LL_RCC_PLL_ConfigDomain_SYS() argument
1221 …DIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV, Source | PLLMul | PLLDiv); in LL_RCC_PLL_ConfigDomain_SYS()

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