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Searched refs:SCU (Results 1 – 14 of 14) sorted by relevance

/bsp/acm32/acm32f4xx-nucleo/libraries/Device/
A DSystem_ACM32F4.c191 SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (33 << 3); in System_Clock_Init()
201 SCU->PLLCR = (SCU->PLLCR & ~(0xFFFF8)) | (18U << 3); in System_Clock_Init()
240 … SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (1U << 12) | (0U << 16); in System_Clock_Init()
241 SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); in System_Clock_Init()
252 SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); // select XTH in System_Clock_Init()
294 SCU->CCR2 = (SCU->CCR2 & (~0x7FFU)) | (lu32_sysdiv-1) | (lu32_pclk_div_para << 8); in System_Clock_Init()
534 SCU->RCR &= (~BIT29); in System_Reset_MCU()
670 if ((SCU->RSR) & (1U << i)) in System_Return_Last_Reset_Reason()
704 SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5); in System_Set_Buzzer_Divider()
705 SCU->CLKOCR |= BIT23; in System_Set_Buzzer_Divider()
[all …]
A DACM32F4.h778 #define SCU ((SCU_TypeDef *)SCU_BASE) macro
/bsp/acm32/acm32f0x0-nucleo/libraries/Device/
A DSystem_ACM32F0x0.c85 SCU->RCR |= SCU_RCR_REMAP_EN; in System_Init()
163 SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (1U << 12) | (0U << 16); in System_Clock_Init()
167 SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (15U << 3) | (2U << 12) | (0U << 16); in System_Clock_Init()
170 SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); in System_Clock_Init()
175 SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1); in System_Clock_Init()
190 SCU->CCR2 = (SCU->CCR2 & (~0xFF)) | APB_CLK_DIV_0 | (lu32_DIV - 1); in System_Clock_Init()
429 SCU->RCR &= (~BIT29); in System_Reset_MCU()
441 SCU->RCR &= (~BIT30); in System_Reset_MCU()
609 SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5); in System_Set_Buzzer_Divider()
610 SCU->CLKOCR |= BIT23; in System_Set_Buzzer_Divider()
[all …]
A DACM32F0x0.h700 #define SCU ((SCU_TypeDef *)SCU_BASE) macro
/bsp/acm32/acm32f4xx-nucleo/libraries/HAL_Driver/Src/
A DHAL_GPIO.c105 lu32_PollUP = &(SCU->PABPUR); in HAL_GPIO_Init()
106 lu32_PollDown = &(SCU->PABPDR); in HAL_GPIO_Init()
107 lu32_ODEnable = &(SCU->PABODR); in HAL_GPIO_Init()
108 lu32_ADS = &(SCU->PABADS); in HAL_GPIO_Init()
114 lu32_SEL1 = &(SCU->PBSEL1); in HAL_GPIO_Init()
115 lu32_SEL2 = &(SCU->PBSEL2); in HAL_GPIO_Init()
119 lu32_SEL1 = &(SCU->PASEL1); in HAL_GPIO_Init()
120 lu32_SEL2 = &(SCU->PASEL2); in HAL_GPIO_Init()
549 lp32_ADS = &(SCU->PABADS); in HAL_GPIO_AnalogEnable()
562 lp32_ADS = &(SCU->PCDADS); in HAL_GPIO_AnalogEnable()
[all …]
A DHAL_LPUART.c233 SCU->CCR2 &= (~(BIT13 | BIT14) ); // RC32K in LPUART_Clock_Select()
237 SCU->CCR2 = (SCU->CCR2 & (~(BIT13 | BIT14) )) | (BIT13); // XTAL in LPUART_Clock_Select()
241 …SCU->CCR2 = (SCU->CCR2 & (~(BIT11 | BIT12| BIT13 | BIT14) )) | (BIT11 | BIT12 | BIT14); // pclk/3… in LPUART_Clock_Select()
A DHAL_FSUSB.c27 SCU->PABADS = (SCU->PABADS | ( (0x3 << 11)) ); in HAL_FSUSB_MSP_Init()
A DHAL_RTC.c38 SCU->STOPCFG |= (1 << 0); in HAL_RTC_Config()
/bsp/acm32/acm32f0x0-nucleo/libraries/HAL_Driver/Src/
A DHAL_GPIO.c98 lu32_PollUP = &(SCU->PABPUR); in HAL_GPIO_Init()
99 lu32_PollDown = &(SCU->PABPDR); in HAL_GPIO_Init()
100 lu32_ODEnable = &(SCU->PABODR); in HAL_GPIO_Init()
101 lu32_ADS = &(SCU->PABADS); in HAL_GPIO_Init()
107 lu32_SEL1 = &(SCU->PBSEL1); in HAL_GPIO_Init()
108 lu32_SEL2 = &(SCU->PBSEL2); in HAL_GPIO_Init()
112 lu32_SEL1 = &(SCU->PASEL1); in HAL_GPIO_Init()
113 lu32_SEL2 = &(SCU->PASEL2); in HAL_GPIO_Init()
124 lu32_PollUP = &(SCU->PCDPUR); in HAL_GPIO_Init()
489 lp32_ADS = &(SCU->PABADS); in HAL_GPIO_AnalogEnable()
[all …]
A DHAL_LPUART.c218 SCU->CCR2 &= (~(BIT13 | BIT14) ); // RC32K in LPUART_Clock_Select()
222 SCU->CCR2 = (SCU->CCR2 & (~(BIT13 | BIT14) )) | (BIT13); // XTAL in LPUART_Clock_Select()
226 …SCU->CCR2 = (SCU->CCR2 & (~(BIT11 | BIT12| BIT13 | BIT14) )) | (BIT11 | BIT12 | BIT14); // pclk/32 in LPUART_Clock_Select()
A DHAL_TKEY.c107 SCU->RCHCR |= ((15 << 17) | SCU_RCHCR_RC4M_EN); //RC4M TRIM and Enable. in HAL_TKEY_MspInit()
108 while((SCU->RCHCR & SCU_RCHCR_RC4MRDY) == 0x00); in HAL_TKEY_MspInit()
109 SCU->CCR2 |= SCU_CCR2_TKSCLK_SEL; //TKEY use the RC4M as clock. in HAL_TKEY_MspInit()
A DHAL_RTC.c38 SCU->STOPCFG |= (1 << 0); in HAL_RTC_Config()
/bsp/rx/
A Dproject.vpwhist32 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
35 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
38 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
41 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
44 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
47 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
50 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
53 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
56 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
59 …N=0 MN=C/C++ HM=0 MF=33554432 TL=0 MLL=0 ASE=0 LNL=1 LCF=6 CAPS=0 E=0 ESBU2=1 CL="" SC="" SCE= SCU=
[all …]
/bsp/nxp/imx/imx6sx/cortex-a9/cpu/
A DcortexA9_gcc.S193 @ SCU
196 @ SCU offset from base of private peripheral space --> 0x000
200 @ Enables the SCU
206 ldr r1, [r0, #0x0] @ Read the SCU Control Register
260 ldr r0, [r0, #0x004] @ Read SCU Configuration register
302 @ This function invalidates the SCU copy of the tag rams
306 @ - Invalidate SCU copy of TAG RAMs
318 str r1, [r2, #0x0C] @ Write to SCU Invalidate All in Secure State

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