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Searched refs:VAL_MASK_WE (Results 1 – 5 of 5) sorted by relevance

/bsp/rockchip/common/rk_hal/lib/hal/src/pm/
A Dhal_pm_rk2108.c103 pGrf->PVTM_CON0 = VAL_MASK_WE(GRF_PVTM_CON0_PVTM_START_MASK, in PVTM_ClkRateConfig()
501 pPmu->PWRMODE_CON = VAL_MASK_WE(mask, value); in SOC_SleepModeInit()
506 pPmu->BUS_CLR |= VAL_MASK_WE(mask, value); in SOC_SleepModeInit()
513 pPmu->SHRM_CON1 = VAL_MASK_WE(mask, value); in SOC_SleepModeInit()
517 pPmu->BUS_CLR |= VAL_MASK_WE(mask, value); in SOC_SleepModeInit()
522 pPmu->LDO_CON[1] = VAL_MASK_WE(mask, 0x10); in SOC_SleepModeInit()
530 pPmu->PLL_CON = VAL_MASK_WE(mask, 0x07); in SOC_SleepModeInit()
532 pPmu->PLL_CON = VAL_MASK_WE(mask, 0x05); in SOC_SleepModeInit()
539 pPmu->SFT_CON = VAL_MASK_WE(mask, value); in SOC_SleepModeInit()
551 pPmu->WAKEUP_CFG6 = VAL_MASK_WE(mask, value); in SOC_WakeupSourceConfig()
[all …]
/bsp/rockchip/common/rk_hal/lib/hal/src/cru/
A Dhal_cru.c666 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkEnable()
675 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkEnable()
693 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkDisable()
702 CRU->CRU_CLKGATE_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkDisable()
745 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkResetAssert()
750 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 1U << shift); in HAL_CRU_ClkResetAssert()
769 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkResetDeassert()
774 CRU->CRU_SOFTRST_CON[index] = VAL_MASK_WE(1U << shift, 0U << shift); in HAL_CRU_ClkResetDeassert()
809 CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, (divValue - 1U) << shift); in HAL_CRU_ClkSetDiv()
864 CRU->CRU_CLKSEL_CON[index] = VAL_MASK_WE(mask, muxValue << shift); in HAL_CRU_ClkSetMux()
[all …]
A Dhal_cru_rk2108.c71 CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_EN_MASK, in CRU_DcgConfig()
83 CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_STEP1_MASK, in CRU_DcgConfig()
85 CRU->DCG_CON[ch][4] = VAL_MASK_WE(CRU_DCG0_CON4_CFG_STEP2_MASK, in CRU_DcgConfig()
89 CRU->DCG_CON[ch][5] = VAL_MASK_WE(CRU_DCG0_CON5_CFG_LMT_MASK, in CRU_DcgConfig()
102 CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_CTRL_MASK | in CRU_AsConfig()
138 CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_EN_MASK | in HAL_CRU_AsEnable()
143 CRU->AS_CON[ch][1] = VAL_MASK_WE(CRU_AS0_CON1_AS_EN_MASK | in HAL_CRU_AsEnable()
814 CRU->GLB_RST_CON = VAL_MASK_WE(mask, val); in HAL_CRU_WdtGlbRstEnable()
/bsp/rockchip/common/rk_hal/lib/hal/inc/
A Dhal_def.h48 #define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val)) macro
49 #define WRITE_REG_MASK_WE(reg, msk, val) WRITE_REG(reg, (VAL_MASK_WE(msk, val)))
/bsp/rockchip/common/rk_hal/lib/hal/src/
A Dhal_pd.c127 PMU->BUS_IDLE_REQ = VAL_MASK_WE(1U << reqShift, (idle ? 1U : 0U) << reqShift); in PD_IdleRequest()
157 PMU->PWRDN_CON = VAL_MASK_WE(1U << pwrShift, (on ? 0U : 1U) << pwrShift); in PD_PowerOn()

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