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Searched refs:division_factor (Results 1 – 6 of 6) sorted by relevance

/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd20/
A Dgclk.c137 if (config->division_factor > 1) { in system_gclk_gen_set_config()
139 if (((config->division_factor & (config->division_factor - 1)) == 0)) { in system_gclk_gen_set_config()
147 for (mask = (1UL << 1); mask < config->division_factor; in system_gclk_gen_set_config()
159 (config->division_factor) << GCLK_GENDIV_DIV_Pos; in system_gclk_gen_set_config()
A Dclock.c648 gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/clock_samd21_r21_da_ha1/
A Dgclk.c137 if (config->division_factor > 1) { in system_gclk_gen_set_config()
139 if (((config->division_factor & (config->division_factor - 1)) == 0)) { in system_gclk_gen_set_config()
147 for (mask = (1UL << 1); mask < config->division_factor; in system_gclk_gen_set_config()
159 (config->division_factor) << GCLK_GENDIV_DIV_Pos; in system_gclk_gen_set_config()
A Dclock.c714 gclk_conf.division_factor = CONF_CLOCK_GCLK_##n##_PRESCALER; \
/bsp/samd21/sam_d2x_asflib/sam0/drivers/system/clock/
A Dgclk.h152 uint32_t division_factor; member
208 config->division_factor = 1; in system_gclk_gen_get_config_defaults()
/bsp/samd21/board/
A Dboard.c79 config_gclock_gen.division_factor = 1; in configure_dfll_open_loop()

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