Searched refs:mwidth (Results 1 – 6 of 6) sorted by relevance
| /bsp/allwinner/libraries/sunxi-hal/hal/source/ccmu/sunxi/ |
| A D | clk_periph.c | 389 if (divider->mwidth) in sunxi_clk_periph_recalc_rate()
391 div_m = GET_BITS(divider->mshift, divider->mwidth, reg); in sunxi_clk_periph_recalc_rate()
434 div_m = 1 << divider->mwidth; in sunxi_clk_periph_round_rate()
504 div_m = 1 << divider->mwidth; in sunxi_clk_periph_set_rate()
542 …>reg %d divider->mwidth %d divider->nshift %d \n", divider->reg, divider->mwidth, divider->nshift); in sunxi_clk_periph_set_rate()
548 if (divider->mwidth) in sunxi_clk_periph_set_rate()
550 reg = SET_BITS(divider->mshift, divider->mwidth, reg, div_m); in sunxi_clk_periph_set_rate()
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| A D | clk_factors.c | 320 if (config->mwidth) in sunxi_clk_factors_recalc_rate()
322 factor_val.factorm = GET_BITS(config->mshift, config->mwidth, reg); in sunxi_clk_factors_recalc_rate()
427 if (config->mwidth) in sunxi_clk_factors_set_rate()
429 reg = SET_BITS(config->mshift, config->mwidth, reg, factor_val.factorm); in sunxi_clk_factors_set_rate()
520 factor->factorm = (table[index].factor >> f_config->mshift) & ((1 << (f_config->mwidth)) - 1); in sunxi_clk_get_common_factors()
603 factor->factorm = (table[i].factor >> f_config->mshift) & ((1 << (f_config->mwidth)) - 1); in sunxi_clk_com_ftr_sr()
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| A D | clk_periph.h | 52 … .mwidth = _div_mwidth, \
143 u8 mwidth; member
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| A D | clk_factors.h | 76 .mwidth = _mwidth, \
201 u8 mwidth; member
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| /bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Source/ |
| A D | gd32vf103_dma.c | 395 void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth) in dma_memory_width_config() argument
407 ctl |= mwidth; in dma_memory_width_config()
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| /bsp/gd32/risc-v/libraries/GD32VF103_Firmware_Library/GD32VF103_standard_peripheral/Include/ |
| A D | gd32vf103_dma.h | 256 void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
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