| /bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/ |
| A D | hal_soc_eu_periph.h | 140 uint32_t reg_offset = evt/32 * 4; in hal_soc_eu_set_fc_mask() local
141 soc_eu_fc_write(soc_eu_fc_read(reg_offset) & ~(1 << shift), reg_offset); in hal_soc_eu_set_fc_mask()
149 uint32_t reg_offset = evt/32 * 4; in hal_soc_eu_set_pr_mask() local
150 soc_eu_pr_write(soc_eu_pr_read(reg_offset) & ~(1 << shift), reg_offset); in hal_soc_eu_set_pr_mask()
158 uint32_t reg_offset = evt/32 * 4; in hal_soc_eu_set_cl_mask() local
159 soc_eu_cl_write(soc_eu_cl_read(reg_offset) & ~(1 << shift), reg_offset); in hal_soc_eu_set_cl_mask()
167 uint32_t reg_offset = evt/32 * 4; in hal_soc_eu_clear_fc_mask() local
168 soc_eu_fc_write(soc_eu_fc_read(reg_offset) | (1 << shift), reg_offset); in hal_soc_eu_clear_fc_mask()
176 uint32_t reg_offset = evt/32 * 4; in hal_soc_eu_clear_pr_mask() local
177 soc_eu_pr_write(soc_eu_pr_read(reg_offset) | (1 << shift), reg_offset); in hal_soc_eu_clear_pr_mask()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/pwm/ |
| A D | hal_pwm.c | 489 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
491 hal_writel(temp, PWM_BASE + reg_offset); in hal_pwm_control()
500 reg_offset = PWM_PCR + 0x20 * channel; in hal_pwm_control()
503 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
505 hal_writel(temp, PWM_BASE + reg_offset); in hal_pwm_control()
508 reg_offset = PWM_PPR + 0x20 * channel; in hal_pwm_control()
511 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
513 hal_writel(temp, PWM_BASE + reg_offset); in hal_pwm_control()
516 reg_offset = PWM_PPR + 0x20 * channel; in hal_pwm_control()
519 temp = hal_readl(PWM_BASE + reg_offset); in hal_pwm_control()
[all …]
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| /bsp/at91/at91sam9260/platform/ |
| A D | io.h | 27 rt_inline unsigned int at91_sys_read(unsigned int reg_offset) in at91_sys_read() argument
31 return readl(addr + reg_offset); in at91_sys_read()
34 rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value) in at91_sys_write() argument
38 writel(value, addr + reg_offset); in at91_sys_write()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/sound/platform/ |
| A D | sunxi-mad.c | 801 int reg_offset = 0; in sunxi_mad_show_all_regs() local
804 for (reg_offset = 0; reg_offset < 0x6c; reg_offset += 0x10) { in sunxi_mad_show_all_regs()
805 reg_val[0] = snd_mad_read(sunxi_mad, reg_offset + 0x0); in sunxi_mad_show_all_regs()
806 reg_val[1]= snd_mad_read(sunxi_mad, reg_offset + 0x4); in sunxi_mad_show_all_regs()
807 reg_val[2]= snd_mad_read(sunxi_mad, reg_offset + 0x8); in sunxi_mad_show_all_regs()
808 reg_val[3]= snd_mad_read(sunxi_mad, reg_offset + 0xc); in sunxi_mad_show_all_regs()
810 reg_offset, reg_offset+0xc, in sunxi_mad_show_all_regs()
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| /bsp/nxp/imx/imxrt/libraries/drivers/ |
| A D | drv_gpio.c | 97 const rt_int32_t reg_offset[] = variable
594 …IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); in imxrt_pin_mode()
595 …IOMUXC_SetPinConfig(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4,… in imxrt_pin_mode()
607 …IOMUXC_SetPinMux(MUX_BASE + reg_offset[pin] * 4, 0x5U, 0, 0, CONFIG_BASE + reg_offset[pin] * 4, 1); in imxrt_pin_mode()
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| /bsp/nxp/imx/imx6ull-smart/drivers/ |
| A D | drv_pin.c | 202 rt_int8_t port, pin_num, reg_offset; in imx6ull_pin_mode() local
249 reg_offset = gpio_reg_offset[port][pin_num]; in imx6ull_pin_mode()
256 mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; in imx6ull_pin_mode()
257 config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; in imx6ull_pin_mode()
263 mux_base_addr = (rt_uint32_t)&periph->SW_MUX_CTL_PAD[reg_offset]; in imx6ull_pin_mode()
264 config_base_addr = (rt_uint32_t)&periph->SW_PAD_CTL_PAD[reg_offset]; in imx6ull_pin_mode()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/g2d_rcq/ |
| A D | g2d_rcq.h | 54 __u32 reg_offset; /* offset_addr based on g2d_reg_base */ member
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| A D | g2d_mixer.c | 563 rcq_hd->reg_offset = (__u32)(__u64)( in g2d_mixer_mem_setup()
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| /bsp/allwinner/libraries/sunxi-hal/hal/source/sdmmc/ |
| A D | hal_sdhost.c | 270 int32_t __mci_check_bit_clear(struct mmc_host *host, uint32_t reg_offset, uint32_t bit_map);
1210 int32_t __mci_check_bit_clear(struct mmc_host *host, uint32_t reg_offset, uint32_t bit_map) in __mci_check_bit_clear() argument
1214 if(!(mci_readl(host, reg_offset) & bit_map)){ in __mci_check_bit_clear()
1216 (host->reg_base) + reg_offset,\ in __mci_check_bit_clear()
1218 HAL_PR_SZ_L(mci_readl(host, reg_offset)),\ in __mci_check_bit_clear()
1226 (host->reg_base) + reg_offset,\ in __mci_check_bit_clear()
1228 HAL_PR_SZ_L(mci_readl(host, reg_offset)),\ in __mci_check_bit_clear()
1233 (host->reg_base) + reg_offset,\ in __mci_check_bit_clear()
1235 HAL_PR_SZ_L(mci_readl(host, reg_offset)),\ in __mci_check_bit_clear()
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| /bsp/frdm-k64f/device/MK64F12/ |
| A D | fsl_clock.h | 363 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ argument
364 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
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