Searched refs:ulBase (Results 1 – 25 of 112) sorted by relevance

12345

/bsp/lm4f232/Libraries/driverlib/
A D	i2c.c	73 return((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE) || in I2CMasterBaseValid() 74 (ulBase == I2C2_MASTER_BASE) || (ulBase == I2C3_MASTER_BASE) || in I2CMasterBaseValid() 75 (ulBase == I2C4_MASTER_BASE) || (ulBase == I2C5_MASTER_BASE)); in I2CMasterBaseValid() 96 return((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE) || in I2CSlaveBaseValid() 97 (ulBase == I2C2_SLAVE_BASE) || (ulBase == I2C3_SLAVE_BASE) || in I2CSlaveBaseValid() 98 (ulBase == I2C4_SLAVE_BASE) || (ulBase == I2C5_SLAVE_BASE)); in I2CSlaveBaseValid() 116 I2CIntNumberGet(unsigned long ulBase) in I2CIntNumberGet() argument 187 I2CMasterEnable(ulBase); in I2CMasterInitExpClk() 239 I2CSlaveEnable(ulBase); in I2CSlaveInit() 404 HWREG(ulBase + I2C_O_SCSR) = 0; in I2CSlaveDisable() [all …]
A D	uart.c	84 UARTBaseValid(unsigned long ulBase) in UARTBaseValid() argument 86 return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || in UARTBaseValid() 87 (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || in UARTBaseValid() 88 (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || in UARTBaseValid() 89 (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); in UARTBaseValid() 169 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet() 344 UARTDisable(ulBase); in UARTConfigSetExpClk() 395 UARTEnable(ulBase); in UARTConfigSetExpClk() 932 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet() 1007 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet() [all …]
A D	watchdog.c	58 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogRunning() 87 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogEnable() 117 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetEnable() 147 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetDisable() 173 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLock() 200 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogUnlock() 226 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLockState() 260 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadSet() 288 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadGet() 313 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogValueGet() [all …]
A D	timer.c	78 return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || in TimerBaseValid() 79 (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) || in TimerBaseValid() 80 (ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) || in TimerBaseValid() 81 (ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) || in TimerBaseValid() 82 (ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) || in TimerBaseValid() 83 (ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE)); in TimerBaseValid() 398 HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | in TimerControlEvent() 1162 ulBase = TimerIntNumberGet(ulBase); in TimerIntRegister() 1177 IntEnable(ulBase); in TimerIntRegister() 1228 ulBase = TimerIntNumberGet(ulBase); in TimerIntUnregister() [all …]
A D	qei.c	60 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIEnable() 85 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDisable() 131 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIConfigure() 136 HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & in QEIConfigure() 168 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionGet() 195 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionSet() 224 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDirectionGet() 251 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIErrorGet() 280 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityEnable() 306 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityDisable() [all …]
A D	i2s.c	54 I2STxEnable(unsigned long ulBase) in I2STxEnable() argument 59 ASSERT(ulBase == I2S0_BASE); in I2STxEnable() 86 I2STxDisable(unsigned long ulBase) in I2STxDisable() argument 91 ASSERT(ulBase == I2S0_BASE); in I2STxDisable() 137 ASSERT(ulBase == I2S0_BASE); in I2STxDataPut() 190 ASSERT(ulBase == I2S0_BASE); in I2STxDataPutNonBlocking() 245 ASSERT(ulBase == I2S0_BASE); in I2STxConfigSet() 314 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitSet() 342 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitGet() 376 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLevelGet() [all …]
A D	adc.c	95 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntRegister() 140 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntUnregister() 178 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntDisable() 207 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntEnable() 246 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntStatus() 307 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntClear() 335 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceEnable() 363 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceDisable() 436 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceConfigure() 530 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceStepConfigure() [all …]
A D	lpc.c	95 ASSERT(ulBase == LPC0_BASE); in LPCConfigSet() 123 LPCConfigGet(unsigned long ulBase) in LPCConfigGet() argument 128 ASSERT(ulBase == LPC0_BASE); in LPCConfigGet() 158 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressSet() 185 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressGet() 217 ASSERT(ulBase == LPC0_BASE); in LPCStatusGet() 267 ASSERT(ulBase == LPC0_BASE); in LPCSCIAssert() 314 ASSERT(ulBase == LPC0_BASE); in LPCIRQConfig() 367 ASSERT(ulBase == LPC0_BASE); in LPCIRQSet() 405 ASSERT(ulBase == LPC0_BASE); in LPCIRQClear() [all …]
A D	ssi.c	68 SSIBaseValid(unsigned long ulBase) in SSIBaseValid() argument 70 return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) || in SSIBaseValid() 71 (ulBase == SSI2_BASE) || (ulBase == SSI3_BASE)); in SSIBaseValid() 189 ASSERT(SSIBaseValid(ulBase)); in SSIConfigSetExpClk() 246 SSIEnable(unsigned long ulBase) in SSIEnable() argument 251 ASSERT(SSIBaseValid(ulBase)); in SSIEnable() 271 SSIDisable(unsigned long ulBase) in SSIDisable() argument 276 ASSERT(SSIBaseValid(ulBase)); in SSIDisable() 312 ASSERT(SSIBaseValid(ulBase)); in SSIIntRegister() 354 ASSERT(SSIBaseValid(ulBase)); in SSIIntUnregister() [all …]
/bsp/lm3s8962/Libraries/driverlib/
A D	i2c.c	73 return((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE) || in I2CMasterBaseValid() 74 (ulBase == I2C2_MASTER_BASE) || (ulBase == I2C3_MASTER_BASE) || in I2CMasterBaseValid() 75 (ulBase == I2C4_MASTER_BASE) || (ulBase == I2C5_MASTER_BASE)); in I2CMasterBaseValid() 96 return((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE) || in I2CSlaveBaseValid() 97 (ulBase == I2C2_SLAVE_BASE) || (ulBase == I2C3_SLAVE_BASE) || in I2CSlaveBaseValid() 98 (ulBase == I2C4_SLAVE_BASE) || (ulBase == I2C5_SLAVE_BASE)); in I2CSlaveBaseValid() 116 I2CIntNumberGet(unsigned long ulBase) in I2CIntNumberGet() argument 187 I2CMasterEnable(ulBase); in I2CMasterInitExpClk() 239 I2CSlaveEnable(ulBase); in I2CSlaveInit() 404 HWREG(ulBase + I2C_O_SCSR) = 0; in I2CSlaveDisable() [all …]
A D	uart.c	84 UARTBaseValid(unsigned long ulBase) in UARTBaseValid() argument 86 return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || in UARTBaseValid() 87 (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || in UARTBaseValid() 88 (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || in UARTBaseValid() 89 (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); in UARTBaseValid() 169 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet() 344 UARTDisable(ulBase); in UARTConfigSetExpClk() 395 UARTEnable(ulBase); in UARTConfigSetExpClk() 932 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet() 1007 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet() [all …]
A D	watchdog.c	58 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogRunning() 87 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogEnable() 117 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetEnable() 147 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetDisable() 173 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLock() 200 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogUnlock() 226 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLockState() 260 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadSet() 288 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadGet() 313 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogValueGet() [all …]
A D	timer.c	78 return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || in TimerBaseValid() 79 (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) || in TimerBaseValid() 80 (ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) || in TimerBaseValid() 81 (ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) || in TimerBaseValid() 82 (ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) || in TimerBaseValid() 83 (ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE)); in TimerBaseValid() 398 HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | in TimerControlEvent() 1162 ulBase = TimerIntNumberGet(ulBase); in TimerIntRegister() 1177 IntEnable(ulBase); in TimerIntRegister() 1228 ulBase = TimerIntNumberGet(ulBase); in TimerIntUnregister() [all …]
A D	qei.c	60 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIEnable() 85 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDisable() 131 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIConfigure() 136 HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & in QEIConfigure() 168 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionGet() 195 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionSet() 224 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDirectionGet() 251 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIErrorGet() 280 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityEnable() 306 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityDisable() [all …]
A D	i2s.c	54 I2STxEnable(unsigned long ulBase) in I2STxEnable() argument 59 ASSERT(ulBase == I2S0_BASE); in I2STxEnable() 86 I2STxDisable(unsigned long ulBase) in I2STxDisable() argument 91 ASSERT(ulBase == I2S0_BASE); in I2STxDisable() 137 ASSERT(ulBase == I2S0_BASE); in I2STxDataPut() 190 ASSERT(ulBase == I2S0_BASE); in I2STxDataPutNonBlocking() 245 ASSERT(ulBase == I2S0_BASE); in I2STxConfigSet() 314 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitSet() 342 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitGet() 376 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLevelGet() [all …]
A D	adc.c	95 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntRegister() 140 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntUnregister() 178 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntDisable() 207 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntEnable() 246 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntStatus() 307 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntClear() 335 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceEnable() 363 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceDisable() 436 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceConfigure() 530 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceStepConfigure() [all …]
A D	lpc.c	95 ASSERT(ulBase == LPC0_BASE); in LPCConfigSet() 123 LPCConfigGet(unsigned long ulBase) in LPCConfigGet() argument 128 ASSERT(ulBase == LPC0_BASE); in LPCConfigGet() 158 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressSet() 185 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressGet() 217 ASSERT(ulBase == LPC0_BASE); in LPCStatusGet() 267 ASSERT(ulBase == LPC0_BASE); in LPCSCIAssert() 314 ASSERT(ulBase == LPC0_BASE); in LPCIRQConfig() 367 ASSERT(ulBase == LPC0_BASE); in LPCIRQSet() 405 ASSERT(ulBase == LPC0_BASE); in LPCIRQClear() [all …]
/bsp/lm3s9b9x/Libraries/driverlib/
A D	i2c.c	73 return((ulBase == I2C0_MASTER_BASE) || (ulBase == I2C1_MASTER_BASE) || in I2CMasterBaseValid() 74 (ulBase == I2C2_MASTER_BASE) || (ulBase == I2C3_MASTER_BASE) || in I2CMasterBaseValid() 75 (ulBase == I2C4_MASTER_BASE) || (ulBase == I2C5_MASTER_BASE)); in I2CMasterBaseValid() 96 return((ulBase == I2C0_SLAVE_BASE) || (ulBase == I2C1_SLAVE_BASE) || in I2CSlaveBaseValid() 97 (ulBase == I2C2_SLAVE_BASE) || (ulBase == I2C3_SLAVE_BASE) || in I2CSlaveBaseValid() 98 (ulBase == I2C4_SLAVE_BASE) || (ulBase == I2C5_SLAVE_BASE)); in I2CSlaveBaseValid() 116 I2CIntNumberGet(unsigned long ulBase) in I2CIntNumberGet() argument 187 I2CMasterEnable(ulBase); in I2CMasterInitExpClk() 239 I2CSlaveEnable(ulBase); in I2CSlaveInit() 404 HWREG(ulBase + I2C_O_SCSR) = 0; in I2CSlaveDisable() [all …]
A D	uart.c	84 UARTBaseValid(unsigned long ulBase) in UARTBaseValid() argument 86 return((ulBase == UART0_BASE) || (ulBase == UART1_BASE) || in UARTBaseValid() 87 (ulBase == UART2_BASE) || (ulBase == UART3_BASE) || in UARTBaseValid() 88 (ulBase == UART4_BASE) || (ulBase == UART5_BASE) || in UARTBaseValid() 89 (ulBase == UART6_BASE) || (ulBase == UART7_BASE)); in UARTBaseValid() 169 HWREG(ulBase + UART_O_LCRH) = ((HWREG(ulBase + UART_O_LCRH) & in UARTParityModeSet() 344 UARTDisable(ulBase); in UARTConfigSetExpClk() 395 UARTEnable(ulBase); in UARTConfigSetExpClk() 932 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTFlowControlSet() 1007 HWREG(ulBase + UART_O_CTL) = ((HWREG(ulBase + UART_O_CTL) & in UARTTxIntModeSet() [all …]
A D	watchdog.c	58 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogRunning() 87 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogEnable() 117 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetEnable() 147 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogResetDisable() 173 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLock() 200 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogUnlock() 226 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogLockState() 260 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadSet() 288 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogReloadGet() 313 ASSERT((ulBase == WATCHDOG0_BASE) || (ulBase == WATCHDOG1_BASE)); in WatchdogValueGet() [all …]
A D	timer.c	78 return((ulBase == TIMER0_BASE) || (ulBase == TIMER1_BASE) || in TimerBaseValid() 79 (ulBase == TIMER2_BASE) || (ulBase == TIMER3_BASE) || in TimerBaseValid() 80 (ulBase == TIMER4_BASE) || (ulBase == TIMER5_BASE) || in TimerBaseValid() 81 (ulBase == WTIMER0_BASE) || (ulBase == WTIMER1_BASE) || in TimerBaseValid() 82 (ulBase == WTIMER2_BASE) || (ulBase == WTIMER3_BASE) || in TimerBaseValid() 83 (ulBase == WTIMER4_BASE) || (ulBase == WTIMER5_BASE)); in TimerBaseValid() 398 HWREG(ulBase + TIMER_O_CTL) = ((HWREG(ulBase + TIMER_O_CTL) & ~ulTimer) | in TimerControlEvent() 1162 ulBase = TimerIntNumberGet(ulBase); in TimerIntRegister() 1177 IntEnable(ulBase); in TimerIntRegister() 1228 ulBase = TimerIntNumberGet(ulBase); in TimerIntUnregister() [all …]
A D	qei.c	60 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIEnable() 85 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDisable() 131 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIConfigure() 136 HWREG(ulBase + QEI_O_CTL) = ((HWREG(ulBase + QEI_O_CTL) & in QEIConfigure() 168 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionGet() 195 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIPositionSet() 224 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIDirectionGet() 251 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIErrorGet() 280 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityEnable() 306 ASSERT((ulBase == QEI0_BASE) || (ulBase == QEI1_BASE)); in QEIVelocityDisable() [all …]
A D	i2s.c	54 I2STxEnable(unsigned long ulBase) in I2STxEnable() argument 59 ASSERT(ulBase == I2S0_BASE); in I2STxEnable() 86 I2STxDisable(unsigned long ulBase) in I2STxDisable() argument 91 ASSERT(ulBase == I2S0_BASE); in I2STxDisable() 137 ASSERT(ulBase == I2S0_BASE); in I2STxDataPut() 190 ASSERT(ulBase == I2S0_BASE); in I2STxDataPutNonBlocking() 245 ASSERT(ulBase == I2S0_BASE); in I2STxConfigSet() 314 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitSet() 342 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLimitGet() 376 ASSERT(ulBase == I2S0_BASE); in I2STxFIFOLevelGet() [all …]
A D	adc.c	95 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntRegister() 140 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntUnregister() 178 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntDisable() 207 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntEnable() 246 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntStatus() 307 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCIntClear() 335 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceEnable() 363 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceDisable() 436 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceConfigure() 530 ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE)); in ADCSequenceStepConfigure() [all …]
A D	lpc.c	95 ASSERT(ulBase == LPC0_BASE); in LPCConfigSet() 123 LPCConfigGet(unsigned long ulBase) in LPCConfigGet() argument 128 ASSERT(ulBase == LPC0_BASE); in LPCConfigGet() 158 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressSet() 185 ASSERT(ulBase == LPC0_BASE); in LPCStatusBlockAddressGet() 217 ASSERT(ulBase == LPC0_BASE); in LPCStatusGet() 267 ASSERT(ulBase == LPC0_BASE); in LPCSCIAssert() 314 ASSERT(ulBase == LPC0_BASE); in LPCIRQConfig() 367 ASSERT(ulBase == LPC0_BASE); in LPCIRQSet() 405 ASSERT(ulBase == LPC0_BASE); in LPCIRQClear() [all …]

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