Searched refs:GIC_DIST_CONFIG (Results 1 – 10 of 10) sorted by relevance
| /libcpu/aarch64/common/ |
| A D | gic.c | 57 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) macro
194 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
200 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
210 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
410 GIC_DIST_CONFIG(dist_base, i) = 0x0U; in arm_gic_dist_init()
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| A D | gicv3.c | 192 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
198 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
208 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16) >> 1)); in arm_gic_get_configuration()
626 GIC_DIST_CONFIG(dist_base, i) = 0; in arm_gic_dist_init()
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| /libcpu/arm/cortex-a/ |
| A D | gic.c | 55 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) macro
192 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
198 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
208 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
402 GIC_DIST_CONFIG(dist_base, i) = 0x0U; in arm_gic_dist_init()
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| A D | gicv3.c | 200 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
206 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
216 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
517 GIC_DIST_CONFIG(dist_base, i) = 0x0U; in arm_gic_dist_init()
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| A D | gicv3.h | 99 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) macro
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| /libcpu/arm/zynqmp-r5/ |
| A D | gic.c | 46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) macro
162 GIC_DIST_CONFIG(dist_base, i) = 0x0; in arm_gic_dist_init()
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| /libcpu/arm/cortex-r52/ |
| A D | gicv3.c | 199 icfgr = GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq); in arm_gic_set_configuration()
205 GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) = icfgr; in arm_gic_set_configuration()
215 return (GIC_DIST_CONFIG(_gic_table[index].dist_hw_base, irq) >> ((irq % 16U) >> 1U)); in arm_gic_get_configuration()
483 GIC_DIST_CONFIG(dist_base, i) = 0x0U; in arm_gic_dist_init()
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| A D | gicv3.h | 99 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U) macro
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| /libcpu/arm/realview-a8-vmm/ |
| A D | gic.c | 46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) macro
228 GIC_DIST_CONFIG(dist_base, i) = 0x0; in arm_gic_dist_init()
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| /libcpu/aarch64/common/include/ |
| A D | gicv3.h | 98 #define GIC_DIST_CONFIG(hw_base, n) HWREG32((hw_base) + 0xc00U + ((n) / 16U) * 4U) macro
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