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/libcpu/arm/sep4020/
A Dcpu.c17 #warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
/libcpu/risc-v/rv64/
A DSConscript8 ASFLAGS = ' -I ' + cwd
/libcpu/risc-v/common/
A DSConscript8 ASFLAGS = ' -I ' + cwd
/libcpu/arm/cortex-m3/
A Dcontext_gcc.S36 CPSID I
88 CPSID I
163 CPSIE I
A Dcontext_iar.S40 CPSID I
88 CPSID I
162 CPSIE I
A Dcontext_rvds.S39 CPSID I
91 CPSID I
168 CPSIE I
/libcpu/arm/cortex-m0/
A Dcontext_gcc.S35 CPSID I
87 CPSID I
181 CPSIE I
A Dcontext_iar.S40 CPSID I
88 CPSID I
187 CPSIE I
A Dcontext_rvds.S40 CPSID I
92 CPSID I
190 CPSIE I
/libcpu/arm/cortex-m23/
A Dcontext_gcc.S36 CPSID I
88 CPSID I
182 CPSIE I
A Dcontext_iar.S41 CPSID I
89 CPSID I
188 CPSIE I
A Dcontext_rvds.S41 CPSID I
93 CPSID I
191 CPSIE I
/libcpu/arm/cortex-m85/
A Dcontext_gcc.S38 CPSID I
91 CPSID I
214 CPSIE I
/libcpu/m16c/m16c62p/
A Dcontext_iar.asm29 FCLR I
A Dcontext_iar.S29 FCLR I
/libcpu/arm/cortex-m4/
A Dcontext_gcc.S40 CPSID I
94 CPSID I
212 CPSIE I
A Dcontext_iar.S44 CPSID I
93 CPSID I
212 CPSIE I
A Dcontext_rvds.S42 CPSID I
94 CPSID I
210 CPSIE I
/libcpu/arm/cortex-m7/
A Dcontext_gcc.S40 CPSID I
93 CPSID I
218 CPSIE I
A Dcontext_iar.S42 CPSID I
90 CPSID I
209 CPSIE I
A Dcontext_rvds.S41 CPSID I
93 CPSID I
209 CPSIE I
/libcpu/aarch64/common/
A Datomic_aarch64.c57 AARCH64_ATOMIC_OP_RETURN(add, add, I) in AARCH64_ATOMIC_OP_RETURN() argument
/libcpu/arm/cortex-m33/
A Dcontext_gcc.S40 CPSID I
93 CPSID I
259 CPSIE I
/libcpu/arm/lpc214x/
A Dcontext_rvds.S20 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
/libcpu/arm/s3c44b0/
A Dstart_rvds.S17 ; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
27 I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
535 ; I/O Ports definitions
826 ; I/O Configuration

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