Searched refs:Set (Results 1 – 15 of 15) sorted by relevance
| /libcpu/risc-v/common64/ |
| A D | README.md | 10 … | The RISC-V Instruction Set Manual Volume II: p…
13 …内存屏障接口 | The RISC-V Instruction Set Manual Volume II: p…
14 … | The RISC-V Instruction Set Manual Volume II: p…
16 … | The RISC-V Instruction Set Manual Volume II: p…
19 … | The RISC-V Instruction Set Manual Volume II: p…
20 … | The RISC-V Instruction Set Manual Volume II: p…
21 … | The RISC-V Instruction Set Manual Volume II: p…
22 … | The RISC-V Instruction Set Manual Volume II: p…
25 … | The RISC-V Instruction Set Manual Volume II: p…
26 … | The RISC-V Instruction Set Manual Volume II: p…
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| /libcpu/arm/zynqmp-r5/ |
| A D | cache.c | 187 u32 Way, WayIndex, Set, SetIndex, NumSet; in Xil_DCacheFlush() local
218 Set = 0U; in Xil_DCacheFlush()
225 C7Reg = Way | Set; in Xil_DCacheFlush()
229 Set += (0x00000001U << LineSize); in Xil_DCacheFlush()
231 Set = 0U; in Xil_DCacheFlush()
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| A D | start_gcc.S | 250 @ Set the startup stack for svc
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| /libcpu/mips/common/ |
| A D | entry_gcc.S | 35 MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
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| /libcpu/v850/70f34/ |
| A D | context_iar.S | 78 mov 0x20, r17 ;Set only ID
95 mov 0x60, r17 ;Set both EIPC and ID bits
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| A D | context_iar.asm | 78 mov 0x20, r17 ;Set only ID
95 mov 0x60, r17 ;Set both EIPC and ID bits
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| /libcpu/arm/cortex-r52/ |
| A D | start_iar.S | 266 orr r0, r0, #0x10000 ;@ Set BIT 16 (Set DOOFMACS)
286 orr r0, r0, #0x80 ;@ Set BIT 7 (Disable out-of-order completion
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| A D | start_gcc.S | 89 @ Set the startup stack for svc
432 orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
452 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
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| /libcpu/arm/cortex-r4/ |
| A D | start_gcc.S | 91 @ Set the startup stack for svc
434 orr r0, r0, #0x10000 @ Set BIT 16 (Set DOOFMACS)
454 orr r0, r0, #0x80 @ Set BIT 7 (Disable out-of-order completion
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| A D | start_ccs.asm | 453 orr r0, r0, #0x10000 ; Set BIT 16 (Set DOOFMACS)
476 orr r0, r0, #0x80 ; Set BIT 7 (Disable out-of-order completion
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| /libcpu/arm/arm926/ |
| A D | start_iar.S | 122 ; Set the cpu to SVC32 mode
128 ; Set CO-Processor
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| A D | start_rvds.S | 118 ; Set CO-Processor
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| /libcpu/arm/cortex-m4/ |
| A D | README.md | 41 int "Set max syscall interrupt priority"
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| /libcpu/ti-dsp/c6x/ |
| A D | context.asm | 45 MVC .S2 B0,TSR ; Set GEE and XEN in TSR
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| /libcpu/arm/realview-a8-vmm/ |
| A D | start_gcc.S | 92 @ Set the startup stack for svc
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