Searched refs:a (Results 1 – 11 of 11) sorted by relevance
| /libcpu/mips/common/ |
| A D | mips_addrspace.h | 48 #define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) argument
53 #define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) argument
54 #define XPHYSADDR(a) ((_ACAST64_(a)) & \ argument
73 #define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) argument
74 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) argument
75 #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) argument
76 #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) argument
86 #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) argument
87 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) argument
88 #define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) argument
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| A D | mips_cache.c | 34 rt_ubase_t end, a; in r4k_icache_flush_range() local
49 if (a == end) in r4k_icache_flush_range()
51 a += ic_lsize; in r4k_icache_flush_range()
58 rt_ubase_t end, a; in r4k_icache_lock_range() local
66 if (a == end) in r4k_icache_lock_range()
68 a += ic_lsize; in r4k_icache_lock_range()
74 rt_ubase_t end, a; in r4k_dcache_inv() local
82 if (a == end) in r4k_dcache_inv()
84 a += dc_lsize; in r4k_dcache_inv()
90 rt_ubase_t end, a; in r4k_dcache_wback_inv() local
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| /libcpu/risc-v/common64/ |
| A D | io.h | 18 #define __arch_getl(a) (*(unsigned int *)(a)) argument
19 #define __arch_putl(v, a) (*(unsigned int *)(a) = (v)) argument
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| /libcpu/unicore32/sep6200/ |
| A D | context_gcc.S | 28 mov.a asr, r1
38 mov.a asr, r0
61 mov.a bsr,r4
63 mov.a asr, r4
76 mov.a bsr, r4
78 mov.a asr, r4
92 cmpsub.a r3, #1
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| A D | start_gcc.S | 148 mov.a asr, r0
180 cmpsub.a r12, #0
192 cmpsub.a r0, r1
200 cmpsub.a r0, r1
213 mov.a asr, r1
261 cmpsub.a r1, #1
267 mov.a pc, lr
291 mov.a asr, r0
316 mov.a bsr, r4
318 mov.a asr, r4
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| /libcpu/arm/cortex-m4/ |
| A D | README.md | 4 …y interrupts except abnormal interrupts after disabling interrupts. This is a common problem in th…
51 …INTERRUPT_PRIORITY` is set to 0x01, the system masking only interrupts with a priority of `0x01-0x…
52 - Interrupts with a priority of 0 are not managed by the system and can continue to respond to inte…
53 …I) register for independent interrupt management, note that interrupts with a priority value lower…
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| /libcpu/arm/zynqmp-r5/ |
| A D | xil_mpu.c | 612 #define u32overflow(a, b) ({typeof(a) s; __builtin_uadd_overflow(a, b, &s); }) argument
614 #define u32overflow(a, b) ((a) > ((a) + (b))) argument
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| /libcpu/arm/am335x/ |
| A D | start_iar.s | 48 __vector: ; Make this a DATA label, so that stack usage
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| /libcpu/arm/cortex-r52/ |
| A D | start_iar.S | 51 ; Align stack start to a 4-byte boundary (32-bit word)
56 DCB 0 ; Define a byte of data and clear it to zero
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| /libcpu/ti-dsp/c28x/ |
| A D | context.s | 110 ; and therefore can be used in a function without being saved on stack first
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| /libcpu/sparc-v8/bm3803/ |
| A D | start_gcc.S | 133 bleu,a bss_loop
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