Searched refs:end (Results 1 – 24 of 24) sorted by relevance

/libcpu/mips/gs232/
A D	cache.c	116 while (start < end) in invalidate_writeback_dcache_all() 125 unsigned long start, end; in invalidate_writeback_dcache() local 130 while (start <end) in invalidate_writeback_dcache() 142 while (start < end) in invalidate_icache_all() 153 while (start <end) in invalidate_dcache_all() 166 while (start < end) in init_dcache() 176 unsigned int start, end; in rt_hw_cache_init() local 193 while (start < end) in rt_hw_cache_init() 204 while(start < end) in rt_hw_cache_init() 211 while(start < end) in rt_hw_cache_init() [all …]
A D	cache_gcc.S	134 .end cache_init
/libcpu/mips/common/
A D	mips_cache.c	34 rt_ubase_t end, a; in r4k_icache_flush_range() local 45 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_flush_range() 49 if (a == end) in r4k_icache_flush_range() 58 rt_ubase_t end, a; in r4k_icache_lock_range() local 62 end = ((addr + size) - 1) & ~(ic_lsize - 1); in r4k_icache_lock_range() 66 if (a == end) in r4k_icache_lock_range() 74 rt_ubase_t end, a; in r4k_dcache_inv() local 78 end = ((addr + size) - 1) & ~(dc_lsize - 1); in r4k_dcache_inv() 82 if (a == end) in r4k_dcache_inv() 90 rt_ubase_t end, a; in r4k_dcache_wback_inv() local [all …]
A D	mips_cache.h	179 rt_ubase_t end = start + g_mips_core.dcache_size; in blast_dcache16() local 182 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in blast_dcache16() 189 rt_ubase_t end = start + g_mips_core.dcache_size; in inv_dcache16() local 192 for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) in inv_dcache16() 199 rt_ubase_t end = start + g_mips_core.icache_size; in blast_icache16() local 202 for (addr = start; addr < end; addr += g_mips_core.icache_line_size) in blast_icache16()
A D	mips.inc	49 #endif /* end of __MIPS_INC__ */
A D	asm.h	42 .end function; \
/libcpu/risc-v/t-head/c908/
A D	cache.c	29 static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); 30 static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))… 31 static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"… 32 static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))… 38 for (; i < end; i += L1_CACHE_BYTES) \ 45 static void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument 50 static void dcachel1_wb_range(unsigned long start, unsigned long end) in dcachel1_wb_range() argument 55 static void dcache_inv_range(unsigned long start, unsigned long end) in dcache_inv_range() argument 60 static void dcache_wbinv_range(unsigned long start, unsigned long end) in dcache_wbinv_range() argument 65 static void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
/libcpu/risc-v/t-head/c906/
A D	cache.c	29 static void dcache_wb_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))); 30 static void dcache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))… 31 static void dcache_wbinv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"… 32 static void icache_inv_range(unsigned long start, unsigned long end) __attribute__((optimize("O0"))… 38 for (; i < end; i += L1_CACHE_BYTES) \ 45 static void dcache_wb_range(unsigned long start, unsigned long end) in dcache_wb_range() argument 50 static void dcache_inv_range(unsigned long start, unsigned long end) in dcache_inv_range() argument 55 static void dcache_wbinv_range(unsigned long start, unsigned long end) in dcache_wbinv_range() argument 60 static void icache_inv_range(unsigned long start, unsigned long end) in icache_inv_range() argument
/libcpu/aarch64/common/
A D	cache_ops.c	15 void __asm_flush_dcache_range(rt_size_t start, rt_size_t end); 16 void __asm_invalidate_dcache_range(rt_size_t start, rt_size_t end); 17 void __asm_invalidate_icache_range(rt_size_t start, rt_size_t end);
A D	setup.c	231 platform_mem_region.end = fdt_end; in rt_hw_common_setup() 254 init_page_region.end = init_page_end - pv_off; in rt_hw_common_setup() 259 platform_mem_region.end = RT_ALIGN(platform_mem_region.end, ARCH_PAGE_SIZE); in rt_hw_common_setup() 263 platform_mem_desc.vaddr_end = platform_mem_region.end - pv_off - 1; in rt_hw_common_setup()
/libcpu/arm/zynqmp-r5/
A D	cache.c	141 u32 end; in Xil_DCacheInvalidateRange() local 151 end = tempadr + len; in Xil_DCacheInvalidateRange() 152 tempend = end; in Xil_DCacheInvalidateRange() 262 u32 end; in Xil_DCacheFlushRange() local 273 end = LocalAddr + len; in Xil_DCacheFlushRange() 276 while (LocalAddr < end) in Xil_DCacheFlushRange() 384 u32 end; in Xil_ICacheInvalidateRange() local 394 end = LocalAddr + len; in Xil_ICacheInvalidateRange() 400 while (LocalAddr < end) in Xil_ICacheInvalidateRange()
A D	xil_mpu.c	619 UINTPTR Basephysaddr = 0, end = Physaddr + size; in Xil_MemMap() local 630 if ((Basephysaddr + Regionsize) >= end) in Xil_MemMap()
/libcpu/xilinx/microblaze/
A D	context_gcc.S	42 .end rt_hw_interrupt_disable 54 .end rt_hw_interrupt_enable 95 .end rt_hw_context_switch 114 .end rt_hw_context_switch_to 140 .end rt_hw_context_switch_interrupt 219 .end _interrupt_handler
/libcpu/blackfin/bf53x/
A D	context_vdsp.S	28 _rt_hw_interrupt_disable.end: 41 _rt_hw_interrupt_enable.end: 159 _interrupt_thread_switch.end:
/libcpu/arm/armv6/
A D	arm_entry_gcc.S	76 .word 0x00000000 @ end mask 77 .word 0x00000000 @ end opcode 92 cmp r7, #0 @ end mask?
/libcpu/mips/pic32/
A D	context_gcc.S	136 .end CoreSW0Handler
/libcpu/ti-dsp/c6x/
A D	vector.asm	95 .end
A D	context.asm	351 .end
A D	intexc.asm	263 .end
/libcpu/arm/arm926/
A D	context_rvds.S	91 end
A D	start_iar.S	129 ; little-end，disbale I/D Cache MMU, vector table is 0x00000000
A D	start_rvds.S	119 ; little-end，disbale I/D Cache MMU, vector table is 0x00000000
/libcpu/ti-dsp/c28x/
A D	context.s	360 .end
/libcpu/unicore32/sep6200/
A D	start_gcc.S	114 .word __bss_start @ load end address

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