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/libcpu/ia32/
A Dcpuport.c20 rt_base_t level; in rt_hw_interrupt_disable() local
22 __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); in rt_hw_interrupt_disable()
23 return level; in rt_hw_interrupt_disable()
26 void rt_hw_interrupt_enable(rt_base_t level) in rt_hw_interrupt_enable() argument
28 __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); in rt_hw_interrupt_enable()
/libcpu/arm/cortex-r52/
A Dcpuport.c31 rt_uint32_t level; in rt_hw_cpu_shutdown() local
35 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
36 while (level) in rt_hw_cpu_shutdown()
A Dcp15_gcc.S62 mov r10, #0 @ start clean at cache level 0
64 add r2, r10, r10, lsr #1 @ work out 3x current cache level
67 cmp r1, #2 @ see what cache we have at this level
69 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
94 mov r10, #0 @ swith back to cache level 0
95 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
103 ands r3, r0, #0x7000000 @ get level of coherency
/libcpu/risc-v/common64/
A DREADME.md10 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
13 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
14 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
16 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
19 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
20 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
21 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
22 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
25 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
26 … The RISC-V Instruction Set Manual Volume II: privileged supervisor-level ISA version 1.12 …
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A Dmmu.c230 if (level > 0) in _unmap_pte()
241 pentry = lvl_entry[--level]; in _unmap_pte()
438 static inline uintptr_t _get_level_size(int level) in _get_level_size() argument
465 *level = 1; in _query()
475 *level = 2; in _query()
484 *level = 3; in _query()
511 int level; in rt_hw_mmu_v2p() local
512 rt_ubase_t *pte = _query(aspace, vaddr, &level); in rt_hw_mmu_v2p()
564 int level; in rt_hw_mmu_control() local
575 rt_base_t *pte = _query(aspace, vaddr, &level); in rt_hw_mmu_control()
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/libcpu/aarch64/common/
A Dmmu.c70 int level; in _kenrel_unmap_4K() local
81 for (level = 0; level < MMU_TBL_LEVEL_NR; level++) in _kenrel_unmap_4K()
109 level--; in _kenrel_unmap_4K()
129 level--; in _kenrel_unmap_4K()
138 int level; in _kernel_map_4K() local
154 for (level = 0; level < MMU_TBL_PAGE_4k_LEVEL; level++) in _kernel_map_4K()
206 int level; in _kernel_map_2M() local
223 for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; level++) in _kernel_map_2M()
637 int level; in _map_single_page_2M() local
651 for (level = 0; level < MMU_TBL_BLOCK_2M_LEVEL; level++) in _map_single_page_2M()
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/libcpu/sim/win32/
A Dstartup_msvc.c82 const char *level; member
115 table->level = ((struct rt_init_desc *)ptr_begin)->level; in rt_init_objects_sort()
138 if (rt_strcmp(rt_init_table[index_j].level, rt_init_table[index_j + 1].level) > 0) in rt_init_objects_sort()
167 if (rt_strcmp(rt_init_table[index_i].level, lv_end) >= 0) in rt_components_board_init()
198 if (rt_strcmp(rt_init_table[index_i].level, lv_start) <= 0) in rt_components_init()
202 if (rt_strcmp(rt_init_table[index_i].level, lv_end) >= 0) in rt_components_init()
/libcpu/sparc-v8/bm3803/
A Dvector_gcc.S48 TRAP_ENTRY(_ISR_Handler) ! 12 interrupt level 2
49 TRAP_ENTRY(_ISR_Handler) ! 13 interrupt level 3
50 TRAP_ENTRY(_ISR_Handler) ! 14 interrupt level 4
51 TRAP_ENTRY(_ISR_Handler) ! 15 interrupt level 5
52 TRAP_ENTRY(_ISR_Handler) ! 16 interrupt level 6
53 TRAP_ENTRY(_ISR_Handler) ! 17 interrupt level 7
54 TRAP_ENTRY(_ISR_Handler) ! 18 interrupt level 8
55 TRAP_ENTRY(_ISR_Handler) ! 19 interrupt level 9
56 TRAP_ENTRY(_ISR_Handler) ! 1A interrupt level 1
57 TRAP_ENTRY(_ISR_Handler) ! 1B interrupt level 11
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/libcpu/arm/cortex-a/
A Dcpuport.c79 rt_base_t level; in rt_hw_cpu_shutdown() local
82 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
83 while (level) in rt_hw_cpu_shutdown()
/libcpu/unicore32/sep6200/
A Dcpu.c265 rt_base_t level; in rt_hw_cpu_shutdown() local
268 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
270 while (level) in rt_hw_cpu_shutdown()
A Dserial.c53 rt_base_t level; in rt_serial_savechar() local
56 level = rt_hw_interrupt_disable(); in rt_serial_savechar()
72 rt_hw_interrupt_enable(level); in rt_serial_savechar()
99 rt_base_t level; in rt_serial_read() local
110 level = rt_hw_interrupt_disable(); in rt_serial_read()
117 rt_hw_interrupt_enable(level); in rt_serial_read()
/libcpu/xilinx/microblaze/
A Dserial.c50 rt_base_t level; in rt_hw_serial_isr() local
64 level = rt_hw_interrupt_disable(); in rt_hw_serial_isr()
88 rt_hw_interrupt_enable(level); in rt_hw_serial_isr()
161 rt_base_t level; in rt_serial_read() local
164 level = rt_hw_interrupt_disable(); in rt_serial_read()
178 rt_hw_interrupt_enable(level); in rt_serial_read()
183 rt_hw_interrupt_enable(level); in rt_serial_read()
/libcpu/aarch64/common/include/
A Dcpu.h38 #define MPIDR_LEVEL_SHIFT(level) (((1 << (level)) >> 1) << MPIDR_LEVEL_BITS_SHIFT) argument
40 #define MPIDR_AFFINITY_LEVEL(mpidr, level) (((mpidr) >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MAS… argument
/libcpu/mips/gs264/
A Dmmu.c212 rt_base_t level; in rt_hw_mmu_map_init() local
235 level = rt_hw_interrupt_disable(); in rt_hw_mmu_map_init()
254 rt_hw_interrupt_enable(level); in rt_hw_mmu_map_init()
712 rt_base_t level; in rt_hw_mmu_map() local
716 rt_hw_interrupt_enable(level); in rt_hw_mmu_map()
723 rt_base_t level; in rt_hw_mmu_map_auto() local
727 rt_hw_interrupt_enable(level); in rt_hw_mmu_map_auto()
734 rt_base_t level; in rt_hw_mmu_unmap() local
738 rt_hw_interrupt_enable(level); in rt_hw_mmu_unmap()
797 rt_base_t level; in rt_hw_mmu_v2p() local
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/libcpu/ppc/ppc405/
A Dinterrupt.c80 rt_base_t level; in rt_hw_interrupt_install() local
89 level = rt_hw_interrupt_disable(); /* lock interrupts to prevent races */ in rt_hw_interrupt_install()
95 rt_hw_interrupt_enable(level); in rt_hw_interrupt_install()
A Dserial.c118 rt_base_t level; in rt_serial_read() local
121 level = rt_hw_interrupt_disable(); in rt_serial_read()
135 rt_hw_interrupt_enable(level); in rt_serial_read()
140 rt_hw_interrupt_enable(level); in rt_serial_read()
233 rt_base_t level; in rt_serial_isr() local
238 level = rt_hw_interrupt_disable(); in rt_serial_isr()
255 rt_hw_interrupt_enable(level); in rt_serial_isr()
/libcpu/arm/am335x/
A Dcpu.c187 rt_base_t level; in rt_hw_cpu_shutdown() local
190 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
191 while (level) in rt_hw_cpu_shutdown()
/libcpu/arm/arm926/
A Dcpuport.c166 rt_base_t level; in rt_hw_cpu_shutdown() local
169 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
171 while (level) in rt_hw_cpu_shutdown()
/libcpu/blackfin/bf53x/
A Dserial.c60 rt_base_t level; in rt_serial_savechar() local
63 level = rt_hw_interrupt_disable(); in rt_serial_savechar()
79 rt_hw_interrupt_enable(level); in rt_serial_savechar()
108 rt_base_t level; in rt_serial_read() local
119 level = rt_hw_interrupt_disable(); in rt_serial_read()
126 rt_hw_interrupt_enable(level); in rt_serial_read()
/libcpu/arm/sep4020/
A Dserial.c55 rt_base_t level; in rt_serial_savechar() local
58 level = rt_hw_interrupt_disable(); in rt_serial_savechar()
74 rt_hw_interrupt_enable(level); in rt_serial_savechar()
101 rt_base_t level; in rt_serial_read() local
112 level = rt_hw_interrupt_disable(); in rt_serial_read()
119 rt_hw_interrupt_enable(level); in rt_serial_read()
/libcpu/arm/dm36x/
A Dcpuport.c165 rt_base_t level; in rt_hw_cpu_shutdown() local
168 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
170 while (level) in rt_hw_cpu_shutdown()
/libcpu/arm/armv6/
A Dcpuport.c167 rt_base_t level; in rt_hw_cpu_shutdown() local
170 level = rt_hw_interrupt_disable(); in rt_hw_cpu_shutdown()
172 while (level) in rt_hw_cpu_shutdown()
/libcpu/arm/AT91SAM7S/
A Dserial.c75 rt_base_t level; in rt_hw_serial_isr() local
99 level = rt_hw_interrupt_disable(); in rt_hw_serial_isr()
118 rt_hw_interrupt_enable(level); in rt_hw_serial_isr()
232 rt_base_t level; in rt_serial_read() local
235 level = rt_hw_interrupt_disable(); in rt_serial_read()
249 rt_hw_interrupt_enable(level); in rt_serial_read()
254 rt_hw_interrupt_enable(level); in rt_serial_read()
/libcpu/m16c/m16c62p/
A Dcpuport.c105 void rt_hw_interrupt_enable(rt_base_t level) in rt_hw_interrupt_enable() argument
109 temp = level & 0xffff; in rt_hw_interrupt_enable()
/libcpu/arm/cortex-m4/
A DREADME.md17 rt_base_t level = __get_BASEPRI();
23 return level;
26 void rt_hw_interrupt_enable(rt_base_t level)
28 __set_BASEPRI(level);

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