Searched refs:x5 (Results 1 – 13 of 13) sorted by relevance
| /libcpu/aarch64/common/include/ |
| A D | hypercall.h | 22 rt_uint64_t x3, rt_uint64_t x4, rt_uint64_t x5, rt_uint64_t x6, rt_uint32_t w7) in rt_hw_hypercall() argument
26 arm_smccc_hvc(w0, x1, x2, x3, x4, x5, x6, w7, &res, RT_NULL); in rt_hw_hypercall()
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| A D | vector_gcc.h | 26 stp x4, x5, [sp, #-0x10]!
80 ldp x4, x5, [sp], #0x10
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| A D | armv8.h | 139 rt_uint64_t x5; member
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| /libcpu/risc-v/rv64/ |
| A D | trap.c | 22 uint64_t x5; member
60 …x5 (t0 : Temporary ) ==> 0x%08x%08x\n", esf->x5 >> 32 , esf->x5 & UINT32_MA… in print_stack_frame()
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| /libcpu/risc-v/t-head/c908/ |
| A D | opcode.h | 76 #define OPC_DCACHE_CVA(rs1) __OPC_INSN_FORMAT_CACHE(0x1, x5, rs1)
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| /libcpu/aarch64/common/mp/ |
| A D | context_gcc.h | 50 ldp x4, x5, [sp], #0x10
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| /libcpu/aarch64/cortex-a/ |
| A D | entry_point.S | 135 mrs x5, mpidr_el1
141 and x0, x5, x4
153 str x5, [x1, #-8]
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| /libcpu/risc-v/common64/ |
| A D | startup_gcc.S | 49 li x5, 0
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| A D | stackframe.h | 90 STORE x5, 5 * REGBYTES(sp)
265 LOAD x5, 5 * REGBYTES(sp)
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| /libcpu/risc-v/common/ |
| A D | interrupt_gcc.S | 66 STORE x5, 5 * REGBYTES(sp)
142 LOAD x5, 5 * REGBYTES(sp)
273 STORE x5, 5 * REGBYTES(sp)
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| A D | context_gcc.S | 150 STORE x5, 5 * REGBYTES(sp)
248 LOAD x5, 5 * REGBYTES(sp)
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| /libcpu/aarch64/common/ |
| A D | cache.S | 42 lsl x7, x6, x5
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| A D | trap.c | 157 …:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (… in rt_hw_show_register()
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