Searched refs:zero (Results 1 – 15 of 15) sorted by relevance
| /libcpu/mips/common/ |
| A D | entry_gcc.S | 34 MTC0 zero, CP0_CAUSE
35 MTC0 zero, CP0_STATUS # Set CPU to disable interrupt.
55 sw zero, 0(t0)
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| A D | mips.inc | 14 #define zero $0 /* wired zero */
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| A D | asm.h | 304 #define SSNOP sll zero, zero, 1
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| A D | context_gcc.S | 104 LONG_S zero, 0(k0) /* clear flag */
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| A D | mips_regs.h | 21 #define zero $0 /* wired zero */ macro
62 #define zero $0 /* wired zero */ macro
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| /libcpu/risc-v/common64/ |
| A D | interrupt_gcc.S | 39 csrw sscratch, zero
56 csrrc a1, stval, zero
66 sw zero, 0(s0)
88 csrw sscratch, zero
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| A D | startup_gcc.S | 96 csrw sscratch, zero
102 beq a0, zero, 1f
118 mv s0, zero
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| /libcpu/mips/pic32/ |
| A D | context_gcc.S | 30 addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
95 addiu t1, zero, -257 /* t1 = ~(1<<8) */
115 addiu t1,zero,0x02 /* t1 = (1<<2) */
119 sw zero, 0(k0) /* clear flag */
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| /libcpu/nios/nios_ii/ |
| A D | vector.S | 15 beq r4,zero,no_need_context
20 mov r5, zero
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| A D | context_gcc.S | 28 wrctl status, zero /* disable interrupt */
86 stw zero,%gprel(rt_thread_switch_interrupt_flag)(gp)
214 bne r2,zero,_from_thread_not_change
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| /libcpu/ti-dsp/c28x/ |
| A D | context.s | 14 ; 2022-10-15 guyunjie add zero-latency interrupt
57 #error ZERO_LATENCY_INT_MASK must be defined for zero latency interrupt
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| /libcpu/risc-v/common/ |
| A D | interrupt_gcc.S | 116 sw zero, 0(t0)
342 sw zero, 0(s0)
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| /libcpu/mips/gs232/ |
| A D | cache_gcc.S | 173 mtc0 zero, CP0_TAGLO
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| /libcpu/arm/cortex-r52/ |
| A D | start_iar.S | 56 DCB 0 ; Define a byte of data and clear it to zero
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| /libcpu/arm/sep4020/ |
| A D | start_rvds.S | 282 BIC R4, R4, #0x80 ; set bit7 to zero
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